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When Vcc falls below lV, the TS809/810/809R/810R RESET output no longer sinks current - it becomes an open circuit. Therefore, high impedance CMOS logic input connected to RESET can drift to undetermined voltages. This present no problem in most applications since most hjP and other circuitry is inoperative with Vcc below lV.However, in applications where RESET must be valid down to OV, adding a pull down resistor to RESET causes and stray leakage currents to flow to ground, holding RESET low (Figure 2.) R1's value is not critical; 100K is large enough not to load RESET and small enough to pull RESET to ground. For the TS809/810/809R/810R if RESET is required to remain valid for Vcc<lV.