Scanning is achieved by means of a digital shift register. The shift register is driven by complimentary square wave clocks, oi and e2. The clock amplitude should be equal to VDD - VSS. With VDD = 5V and VSS = OV. the clock inputs will be HCMOS compatible. Since each photodiode is read out on the positive transition of c,2. the frequency of the clock signal should be set equal to the desired video data rate.
Horizontal SYNC input up t0 150 KHz. On-chip PLL circuitry up t0 150 MHz. Minimum timing measurement among HFLB, VFLB, RIN, GIN and BIN for auto sizing. Full screen self-test pattern generator. Programmable Hor. resolutions up t0 1524 dots per line. Full-screen display consists of 15 (rows) by 30 (columns) Two font size 12x16 0r 12x18 dot matrix per character. True totally 512 mask ROM fonts including 496 standard fonts and 16 multi-color fonts. Double character height and/or width control. Programmable positioning for display screen center. Character bordering, shadowing and blinking effect. Programmable character height (18 t0 71 lines) control. Row to row spacing control to avoid expansion distortion. 4 programmable windows with multi-level operation. Shadowing on windows with programmable shadow width/height/color. Programmable adaptive approach to handle H, V sync collision automatically by hardware. Software clears bit for full-screen erasing. Fade-in/fade-out or blending-in/blending-out effects. 5-channel/8-bit PWM D/A converter output. Compatible with SPI bus or I2C interface with slave address 7AH/7BH (slave address is mask option). 16-pin, 20-pin or 24-pin PDIP package.
| CHARACTERISTIC | SYMBOL | RATING | UNIT |
| Collector-Base Voltage | VCBO | 35 | V |
| Collector-Emitter Voltage | VCEO | 30 | V |
| Emitter-Base Voltage | VEBO | 5 | v |
| Collector Current | IC | 800 | mA |
| Base Current | IB | 160 | mA |
| Collector Power Dissipation | PC | 600 | mW |
| Junction Temperature | Tj | 150 | C |
| Storage Temperature Range | Tstg | - 55150 | C |
| | | |
