| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| RS2501M | RECTRON/台产 | 扁桥 | 07+ | 价格优势，厂价直销 | 38000 |
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| RS2501M | RECTRON/台产 | 扁桥 | 07+ | 价格优势，厂价直销 | 38000 |
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RS2501M Datasheet
RS2501M Price The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the WS7106 0r the WS7107, When the analog COMMON is used as a reference, a nominal +2V full- scale integrator swing is fine. For the WS7107 with +5V supplies and analog COMMON tied to supply ground, a +3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for CINT are 0.22ccF and O.10 F, respectively. Of course, if different oscillator frequen- cies are used, these values should be changed in inverse proportion to maintain the same output swing. RS2501M on stock Active Voltage Programming: Special precautions should be taken when maHng changes to the voltage control progam code while the output is active. It is recommended that the ISR be powered down or held placed in standby Changes made to the program code while Vout is active induces high current transients through the device. This is the result of the electrolytic output capacitors being either charged or discharged to the new output voltage set-point. The transient current can be minimized by making only incremental changes to the binary code, i.e. one LSB at a time. A minimum of 100ps settling time between each program state is also recom- mended. MaHng non-mcremental changes to VID3 and VID4 with the output enabled is discouraged. The tran- sients induced may activate the module's over-current protection. If the program code cannot be asserted prior to power-up, pull pin 6, STBY', to GND during the period that the input voltage is applied. The release of pin 6 will then to allow the device to initiate a soft-start power-up to the program voltage. The Timer can be programmed to count up t0 255 time intervals. Each time interval can be either lT, 8T, 64T or 1024T incre ments, where T is the system clock period. When a full count is reached, an interrupt flag is set to logic "1'. After the interrupt flag is set the internal clock begins counting down at the system clock rate to a maximum of -255T. Thus. after the interrupt flag is set, a Read of tha timer will tell how long since the flag was set up to a maximum of 255T. |
