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I vcc = 2.3 V t0 3.6 V VI = 5.5 v

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RS1A23D10F0 Datasheet

Notes: 1. The Standby/Inhibit control logic is similar for all Power Trends' modules, but the flexibility and threshold tolerances will be different. For specific information on this function for other regulator models, consult the applicable application note.
RS1A23D10F0 Price

				Ta= 25aC			Ta = - 40~850C
PARAMETER	SYMBOL	I n) i lui\iui i IUI-J	Vcc (V)	MIN.	TYP.	MA×	MIN.	MA×	UNIT
Output Transition Time	tTLH tTHL		2.0 4.5 6.0		30 8 7	75 1 5 13		95 19 16
Propagation Delay Time ( CK- Q, Q)	tpLH tpHL		2.0 4.5 6.0		48 14 12	125 25 21		1 55 31 26	ns
Propagation Delay Time (CLR-Q, Q)	tpLH tpHL		2.0 4.5 6.0		52 1 5 13	140 28 24		175 35 30	ns
Maximum Clock Frequency	fMAX		2.0 4.5 6.0	6 31 37	23 70 80		5 25 30		MHz
Input Capacitance	CIN				5	10		10
Power Dissipation Capacitance	CPD (1)				33				pF

RS1A23D10F0 on stock

The output clock is modulated with a waveform depicted in Figure 6. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is +0.45% or -0.6% of the se- lected frequency. Figure 6 details the Cypress spreading pat- tern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for de- tails on these devices.

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