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RS-2B101 Datasheet

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SYMBOL PARAMETER CONDITIONS MAX. UNIT

VF forward voltage IF=10 mA l V

IR reverse current V R= 25 V 50 nA V R= 20 V; T amb=750C 1 cd\

C d diode capacitance f = 1 MHz; V R= 6 V; note l; see Fig.1 1.2 pF

r D diode forward resistance I F= 2 mA; f = 100 MHz; note l; see Fig.2 0.7

RS-2B101 on stock

Symbol	Parameter	Test Conditions	Min	Typ.	Max	Unit
ISD ISDM	Source-drain Current Source-drain Current (pulsed)				5 20	A A
VsD	Forward On Voltage	ISD = 5A VGS = 0			1.2	V
trr Qrr IRRM	Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current	ISD = 5 A di/dt = 100 A/ccS Vr = 20 V Tj = 150 0C (see test circuit, fig.5)		tbd tbd tbd		ns nC A

Due to the high switching speeds of ECL outputs, transmission line design must be used to interconnect components. To ensure optimum signal fidelity, both data outputs (RD+/RD-) should be terminated identi- cally. The signal lines connecting the data outputs to the next device should be equal in length and have matched impedances. Controlled impedance stripline or microstrip construction must be used to preserve the quality of the signal into the next component and to minimize reflections back into the receiver, which could degrade its performance. Excessive ringing due to reflections caused by improperly terminated signal lines makes it difficult for the component receiving these signals to decipher the proper logic levels and can cause transitions to occur where none were intended. Also, by minimizing high-frequency ringing, possible EMI problems can be avoided.

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