RRC4020-150MX Datasheet| | | | | | | | | | | | | | | | | | scsOp (non-re | betitive | bulse) | | | | | | | | | | | | | | | | | | | l | | | RBSOA (Repeti : .i. | tive pulsje) : . i | | | | | | | | | |
RRC4020-150MX Price| SYMBOL | TYPE | DESCRIPTION | | CK, CK | Input | Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. | | CKE | Input | Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions_except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. | | CS | Input | Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. | | RAS, CAS, WE | Input | Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. | | LDM,(U)DM | Input | Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load- ing. For the x16, LDM corresponds to the data on DQO-DQ7 ; UDM correspons to the data on DQ8-DQ15. | | BAO, BA1 | Input | Bank Addres Inputs : BAO and BAl define to which bank an ACTIVE, READ, WRITE or PRE- CHARGE command is being applied. | | An0 | Input | Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BAO, BAl. The address inputs also provide the op-code during a MODE REGISTER SET command. BAO and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). | | DQ | I/O | Data Input/Output : Data bus | | LDQS,(U)DQS | I/O | Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen- tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQO-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. | | QFC | Output | FET Control : Optional. Output during every Read and Write access. Can be used to control isolation switches on modules. | | NC | | No Connect : No internal electrical connection is present. | | VDDQ | Supply | DQ Power Supply : +2.5V 0.2V. | | VssQ | Supply | DQ Ground. | | VDD | Supply | Power Supply : +2.5V 0.2V (device specific). | | Vss | Supply | Ground | | VREF | Input | SSTL_2 reference voltage. | | | |
RRC4020-150MX on stock| Symbol | Pin Number (P-MQFP-80) | I/O*) | UnCtlOn | | XTAL2 | 36 | | XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTALl is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. | | XTAL1 | 37 | | XTAL1 Output of the inverting oscillator amplifier. | | P2.O-P2.7 | 38-45 | I/O | Port 2 is an 8-bit quasi-bidirectional l/0 port with internal pullup resistors. Port 2 pins that have l's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing l's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. | | PSEN | 47 | O | The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. | | ALE | 48 | O | The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. | | | | |
| ltems | Symbols | Test Conditions | Min | Fyp. | Max. | Units | | | Rir, {i-U | lGBT | | | 0.116 | | | Thermal Resistance | Rir, (j-c) | Diode | | | 0.222 | oc/w | | Rih Cc-f) | With Thermal compound | | O015 | | | | | | | | |
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