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3AIl inputs are grounded. AO input is driven with O V to +5 V pulse, Al is grounded. The output is monitored. Speeding the edges ofthe AO pulse increases the glitch magnitude due to coupling via the ground plane. Removing the AO and Al terminations will lower the glitch, as does increasing RL. 4D ecreasing RL slightly lowers the bandwidth. Increasing C L significantly lowers the bandwidth (see Figure 1 8). l series with the multiplexer inputs serves to optimize O.l dB flatness, but is not required (see Figure 19.) Siej t~tojlipsSe)t tlaate:s motebr, ot being driven (i.e., AO and Al are logic O, INO is selected); drive all other inputs with VIN = 0.707 V rms and monitor the output at f = 5 and 30 MHz. 2). 'Multiplexer i;edF'gblld l(2): ENABLE = logic l) and allinputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at f = 5 and 30 MHz. RL = 30 I to simu- late RON ofone enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ IO M I ), and the signal couples across the package; the load impedance determines the crosstalk. aVoltage gain decreases for lower values of RL. T he resistive divider formed by the multipilexers enables output resistance (28 I ) and RL causes a gain that increases as RL. decreases (i.e., the voltage gain is approximately 0.97 VN [3% gain error] for RL = 1 kl ). 9Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See N ote 8. Specifications subject to change without notice.