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| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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RR0816P-3013-D-47D Datasheet Parameter Symbol TestCondition min typ max Unit VccforDataRetention VDR CSVcc-0.2V 2.0 - - V Data Retention Current ICCDR Vcc=3.OV, CS > Vcc-0.2V, VIN > OV - 2.4 mA Chip Deselectto Data Retention tCDR See Retention Waveform o - - ns OperationRecoveryTime tR See RetentionWaveform 5 - - ms RR0816P-3013-D-47D Price The S6C0666 adapts the RSDS interface for EMI solution. The internal RSDS receiver block operates the comparison between the transmitted differential input pair data. The input data lines from the timing controller to the RSDS receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs (DxxP / DxxN). The input common mode voltage range at the RSDS receiver is l.2 V. The differential data and clock signals from the panel timing controller arrive at the S6C0666 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). The nominal peak to peak swing of this data is 200 mV across a termination resistor. RR0816P-3013-D-47D on stock where SF and M are as defined in the previous section, Figures 2 and 3. Typically, RSENSE is chosen between o I and 20 I . Current limit is at a minimum at minimum input voltage and maximum at maximum input voltage. Both conditions should be considered in a design where current limit is important.
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