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RR0816P-1911-B-T5-28H Datasheet
1. Connection 1. +5V power supply to Vccl (Pin 2). 2. Connect back-up capacitor to Vcc2 (Pin 3). 3. Connect a diode between Vccl (Pin 2) and Vcc2 (Pin 3). 4. Connect pulse width setting resistor and capacitor to PC (Pin 4) when using pulse shaver. 5. RE output (Pin 5) is reset signal output and is output when Vcc iS less than 2.15V. 6. When using pulse shaver, PSCONT (Pin 6) is high level. 7. CE output (Pin 7) is for chip enable signal and goes low when power outage is detected. 2. Theory of Operation 1. When +5V power is supplied normally, it is charged to the back-up capacitor via a diode. 2. The back-up capacitor starts back-up if +5V power supply voltage drops for some reason and Vccl goes below 4.2V, and at the same time the CE signal switches the l-chip microcomputer to standby mode, so that it operates on low current consumption. 3. When +5V power supply recovers and goes over 4.2V, an RE output signal of a certain width is output, and this signal resets the l-chip microcomputer. At the same time normal mode starts and the time until crystal oscillator output stabilizes is reset. 4. If +5V power supply does not recover, and back-up capacitor voltage goes below 2.15V, reset is carried out by the RE output signal to prevent the microcomputer from running wild. 3. Setting AC power supply power outage detection 1. Theory of operation for detecting AC voltage AC voltage is rectified and smoothed by the capacitor. This voltage is divided and set at VAC input detection voltage, +2V. At this time the smoothing capacitor and dividing resistor time constants are used to set AC voltage missing waveform. c 2. VAC voltage setting (R1, R2) Set resistor ratio at the midpoint between Rl and R2 so that the voltage to be detected is +2V. Impressed AC voltage There is are no limitations on AC voltage as it is divided by Rl and R2 and applied to PST620. 3. Setting time constants to detect AC voltage (C4, R1+R2) For impressed AC voltage of 5Vrms, and C4 and Rl+R2 time constant of 60mS, set so that AC voltage detects power outage when approximately 2 waveforms are missed. The time constants can be set to detect missing AC waveforms.
RR0816P-1911-B-T5-28H Price

PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
Vss Vcc P0.0-0.7 P1.O-P1.7 P2.O-P2.7 P3.O-P3.7 RST ALE PSEN EANpp XTAL1 XTAL2 20 40 39-32 1-8 1 2 21-28 10-17 10 11 12 13 14 15 16 9 30 29 31 19 18 22 44 43-36 2-9 2 3 24-31 11, 13-19 11 13 14 15 16 17 18 19 10 33 32 35 21 20 16 38 37-30 40-44, 1-3 40 41 18-25 5, 7-13 5 7 8 9 10 11 12 13 4 27 26 29 15 14 I I 1/0 I/O 1/0 I 1/0 1/0 I 0 I I I I O 0 I 0 0 I I 0 Ground: 0 V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port o is an open-drain, bidirectional l/0 port. Port o pins that have ls written to them float and can be used as high-impedance inputs. Port o is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting ls. Port l: Port l is an 8-bit bidirectional l/0 port with internal pull-ups. Port l pins that have ls written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port l pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IlL). Alternate function for Port l: T2 (P1.0): Timer/Counter2 external count input/clockout (see Programmable Clock-Out). T2EX (P1.1): Timer/Counter2 reload/capture/direction control. Port 2: Port 2 is an 8-bit bidirectional l/0 port with internal pull-ups. Port 2 pins that have ls written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: lI¨_) Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting ls. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional l/0 port with internal pull-ups. Port 3 pins that have ls written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IlL). Port 3 also serves the special features of the 89C51/89C52/89C54/89C58, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INTO (P3.2): External interrupt INTl (P3.3): External interrupt TO (P3.4): Timer o external input T1 (P3.5): Timer l external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Vss permits a power-on reset using only an external capacitor to Vcc. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of l/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations OOOOH to the maximum internal memory boundary. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than OFFFH for 4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the 12.00 V programming supply voltage (Vpp) during FLASH programming. Crystal l: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.


RR0816P-1911-B-T5-28H on stock

Parameter Symbol Conditions min typ max Unit
Power supply voltage IDD Average current 55 80 mA
Insertion gain for VOC pin IG fsig=3.579545MHz -9 -5.5 2 dB
Total harmonic distortion for VOC pin THD fsig=3.26486MHz 0.5 2.5 %
Signal-to-noise ratio for VOC pin S/N 3.264 86 MHz output (VP_P)/ noise output (rms) 48 56 dB
Output impedance for VOC pin ZO 300 600
Comb characteristics for VOC pin Coml 3.571678MHz/3.579545MHz (fsc-l/2fH) / (fsJ -35 -25 dB
Com2 3.256993MHz/3.264860MHz (fsc-20.5fH) / (fsc-20fH) -30 -20 dB
3.902097MHz/3.894230MHz (fsc-20.5fH) / (fsc-20fH) -30 -20 dB
Clock leak for VOC pin NC1 3.58-MHz component/main signal in output signal -50 -40 dB
NC2 14.32-MHz component/main signal in output signal -30 -20 dB
Signal bandwidth for VOY pin BW -3 dB for 196.7 kHz 2.5 5.5 MHz
Insertion gain for VOY pin IG fsig=196.7kHz -1.5 1.5 4.5 dB
Total harmonic distortion for VOY pin THD fsig=196.7MHz 1 4.5 %
Signal-to-noise ratio for VOY pin S/N Signal output (P-P)/noise output (rms) 48 56 dB
Clock leak for VOY pin NC3 3.58-MHz component/main signal in output signal -50 -40 dB
NC4 14.32-MHz component/main signal in output signal -20 -10 dB
Delay for VOY pin TD 63.46
Output impedance for VOY pin ZO 250 500
Crosstalk CT fsig=196.7kHz -32 dB


TXV Equivalent 1. Rad Hard TXV Equivalent . Standard Data Package A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet 2. Rad Hard TXV Equivalent . Optional Data Package A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler
 
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