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RQD-1.805 Datasheet

Part Name requency Access Cycle Active Current Standby Current
M5M5V5636GP -16 167MHz 3.8ns 6.Ons 340mA 20mA


RQD-1.805 Price
R WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 09/01
RQD-1.805 on stock
EN/SET Serial Interface (S2CwjreTM) The current source output magnitude is controlled by the EN/SET serial data interface. The interface records rising edges of the EN/SET pin, and decodes them int0 32 individual current level set- tings summarized in the above table. The modulo 32 interface wraps states back to state l after the 32nd clock, so the previous state is achieved by clocking the EN/SET pin 31 times. The counter can be clocked at speeds up t0 1MHz, so intermediate states are not visible. The first rising edge of EN/SET enables the lC and initially sets the output LED current to OdB. Once the final clock cycle is input for the desired brightness level, the EN/SET pin is held high to maintain the device output cur- rent at the programmed level. The device is dis- abled 500ps after the EN/SET pin transitions to a logic low state. The EN/SET timing is designed to accommodate a wide range of data rates. After the first rising edge of EN/SET, the charge pump is enabled and reaches full capacity after the soft start time (tss). During the soft start time, multiple clock pulses may be entered on the EN/SET pin to set the final output current level with a single burst of clocks. Alternatively, the EN/SET clock pulses may be entered one at a time to gradually increase the LED brightness over any desired time period. A constant current is sourced as long as EN/SET remains in a logic high state. The current source outputs are switched off after EN/SET has remained in a low state for at least the tOFF timeout period.
System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these tran- sients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 ~F high frequency, low inherent inductance, ceramic capacitor should be uti- lized for each device. This capacitor should be connected between the Vcc and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 ~F bulk electrolytic capacitor should be utilized, again connected between the Vcc and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.