The internal read and write address pointers are main- tained by the device such that consecutive read opera- tions will access data in the same order as it was written. The Empty flag is asserted (EF = LOW) after the falling edge of R which accesses the last available data in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another word of valid data.
RQ5RW26CA Price| Descriptron | Symbol | min | typ. | max | Unit |
| Channel to Case | Rth(ch-c) | | | 8.33 | oC/w |
| Channel to Ambient | Rth(ch~a) | | | 1 50 | oc/w |
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RQ5RW26CA on stock| lPARAMETER | SYMBOL | MIN | MAX | UNITS |
| Forward Current | IF | 50 | 100 | mA |
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| vo=( | I2V ! | | |
| | l | | |
| | l | | |
| | iA 2 -LOIU l __1__ - | 25YC | |
| | - r - - 75IC |
| C | | | | |
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