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Notes: 1. LOSIN input sets to HIGH, VC is disabled and the VCXO returns to it's nominal center frequency. When sets to LOW, VC to VCXO is enabled. 2. LOS output sets to HIGH, ifno transitions are detected at DATAIN after 256 clock cycles. LOS output sets to LOW as soon as a transition occurs at DATAIN. 3. HIZ input sets LOW, output pins CLKl, CLK2, RCLK, and RDATA buffers are set to high-impedance state. When set to logic high or no connection, the device functions and output pins CLKl, CLK2, RCLK, and RDATA etc. are active.
RPER71H154K2K1C03B Price