The A63P8336 is a high-speed SRAM containing 9M bits of bit synchronous memory, organized as 256K words by 36 bits. The A63P8336 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 256KX36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (AO - A17), all data inputs (l/0i - l/036), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BWl , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode
