| October 1987 FAIRCHIL Revised January 1999 SEMICONDUCTORTki MM74C922 . MM74C923 16-Key Encoder 20-Key Encoder General Description An internal register remembers the last key pressed even after the key is released. The 3-STATE outputs provide for The MM74C922 and MM74C923 CMOS key encoders pro- easy expansion and bus operation and are LPTTL compat- vide all the necessary logic to fully encode an array of ible. SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. Thenit Features encoders also have on-chip pull-up devices which permit switches with up t0 50 kl on resistance to be used. No s 50 k[ maximum switch on resistance diodes in the switch array are needed to eliminate ghost s On or off chip clock switches. The internal debounce circuit needs only a single s On-chip row pull-up devices external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level s 2 key roll-over when a valid keyboard entry has been made. The Data s Keybounce elimination with single capacitor Available output returns to a low level when the entered s Last key register at outputs key is released, even if another key is depressed. The Data s 3-STATE output LPTTL compatible Available will return high to indicate acceptance of the new key after a normal debounce period; this two-key roll-over s Wide supply range: 3V t0 15V is provided between any two switches. s Low power consumption Ordering Code: |
| Order Number | Package Number | Package Description |
| MM74C922N | N18A | 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-O01, 0.300" Wide |
| MM74C922WM | M20B | 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide |
| MM74C923WM | M20B | 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide |
| MM74C923N | N20A | 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-O01, 0.300" Wide |
| Device also available in Tape and Reel Specify by appending suffix letter "X" to the ordering code Connection Diagrams Pin Assignment for DIP Pin Assignment for SOIC |
| 1 ROW Yl - ROWY2 2 ROW y3 3 ROWV4 4 OSCILLATOF1 KEVBOUNCE MASK 6 COLUMNX4 7 COLUMNX3 S | U | 18 ROW Yl - - vcc ROW Y2 - 17 DATA OUT A ROW Y3 - 16 0ATA OUT B ROW Y4 - 15 LJATA OUT C NC - OSCILLATOR - 14 DATA OlJT 0 KEYBOUNCE MASK - 13 iTW COLUMN X4 - 12ATAAVAILABLE COLUMFI X3 - GND - 11 COLUMN Xl | 20 19 18 17 16 15 14 13 12 10 11 | - vcc - DATA OUT A - DATA OUT B - DATA OUT C - DATA OUT D - NC - OUTPUT ENABLE - DATA AVAILABLE - COLUMFI Xl - COLUMFI X2 |
| GND 9 | Top View 10 COLUMN XZ MM74C922 |
| Top View MM94C922 |
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