ADMap-14  > QS74FCT163374CPV

suppliers of QS74FCT163374CPV and PDF data of QS74FCT163374CPV

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
QS74FCT163374CPV IDT    09+    2000 
    Shenzhen Lxpart Technology Co...
  • Contact:davexiao
  • Tel:86-755-27923896
  • Fax:0755-27822696
  • Email: sallychan8@163.com
QS74FCT163374CPV N/A  SSOP-48  01+   
    lissony technology limited
  • Contact:talor
  • Tel:86-755-61329003
  • Fax:
  • Email: lissony@yahoo.cn
QS74FCT163374CPV IDT  SSOP-48  0546+  原装现货,品质为先!  256 
    shanghai deyie Electronics Co...
  • Contact:Mengfancheng
  • Tel:86-21-60896589
  • Fax:086-021-69972619
  • Email: deyidianzi118@126.com
QS74FCT163374CPV IDT    01+    11 
    e-source intl ltd
  • Contact:peter
  • Tel:86-755-82866948
  • Fax:
  • Email: kenvnn@163.com
QS74FCT163374CPV N/A  SSOP48      22 
    RANTLEEASTELECTRONICTRADINGCO
  • Contact:Ms.JessicaWong
  • Tel:86-754-84475086
  • Fax:86-754-84471197
  • Email: rantle-east@vip.163.com

QS74FCT163374CPV Datasheet

Parameter Symbol Min. Max. Unit
Enable cycle time tCYCE 500 ns Fig.6
H" level PWEH 220 ns Fig.6
Enable pulse time L" level PWEL 280 ns Fig.6
Enable rise time / decay time tEr,tEf 20 ns Fig.6
Set-up time RS, R/W,E tAS 40 ns Fig.6
Address hold time tAH 10 ns Fig.6
Data set-up time tDSW 60 ns Fig.6
Data hold time tH 10 ns Fig.6


QS74FCT163374CPV Price
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such Improper use or sale.
QS74FCT163374CPV on stock

--- (DRectangrdarwave0=60 J-L Rectangularwave 0=120' _FL _
(D Rectangularwave 8:180'__L - Sine wave 8 =180' J._
1 §
?L
d} 360' waveL
|


Clock Input Inp ut All inputs and outputs are referenced to the positive edge of this clock.
Clock Phase Enable Inp ul This signal is used to generate an internal clock at '/2 the frequency of the input clock.
Reset InpUf This pin will force all outputs to a high impedence condition, as well as clearing the NSE enable bit.