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QS29FCT520ATZ Datasheet

rINUNL IIU~1 ucopnir nvn
Pin# Syne Input CT RT Voltage Feedback 1 Compensation 1 Curreni Sense 1 Drive Output 1 Gnd Drive Gnd Drive Output 2 Current Sense 2 Compensation 2 Voltage Feedback 2 Drive Output 2 Enable Vref vcc Function A narrow rectangular waveform applied to this input will sychronize the Oscillator. A DC vouage within the range of 2.4V t0 5.5V will inhibit the Oscillator Timing capacitor Cr connects from this pin to ground setting the tree-running Oscillator frequency range. Resistor RT connects from this pin to ground precisely setting the charge current for CT. RT must be between 4.Ok and 16k. This pin is the inverting input of Error Amplifier l. It is normally connected to the switching power supply output through a resistor divider. This pin is the output of Error Amplifier l and is made available for loop compensation. A voltage proportional to the inductor current is connected to this input. PWM l uses this information to terminate conduction ad output switch Ql. This pin directly drives the gate of a power MOSFET Ql. Peak currents up t0 1.OA are sourced and sinked by this pin. This pin is the control circuitry ground return and is connected back to the source ground. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This pin directly drives the gate of a power MOSFET 072 Peak currents up t0 1.OA are sourced and sinked by this pin. A voltage proportional to inductor current is connected to this input. PWM 2 uses this information t0 1erminate conduction of output switch Q2. This pin is the output of Error Amplifier 2 and is made available for loop compensation. This pin in the inverling input of Error Amplifier 2. It is normally connected to the switching power supply output through a resistor divider. A logic low at this input disables Drive Output 2. This is the 5.OV reierence output. It can provide bias for any additional system circuitry This pin is the positive supply of the control IC. The minimum operating voltage range after 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16
start-up is 11V t0 15.5V. ORDERING Ih


QS29FCT520ATZ Price

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QS29FCT520ATZ on stock

SYMBOL PARAMETER 17 110 UNIT
MIN MAX MIN MAX
tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 7 5 2 10 ns
tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 9 5 3 12.5 ns
tco Clock to out delay time 2 6 2 9 ns
tSU_PAL Setup time (from input or feedback node) through PAL 5 8 ns
tSU_PLA Setup time (from input or feedback node) through PAL + PLA 7 10 5 ns
tH Hold time 0 O ns
tCH Clock High time 4 5 ns
tCL Clock Low time 4 5 ns
tR Input rise time 20 20 ns
tF Input fall time 20 20 ns
IMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 125 100 MHz
lMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) 105 64 MHz
IMAX3 Maximum external frequency2 (1/tSUPAL + tCO) 91 59 MHz
tBUF Output buffer delay time 1 5 1.5 ns
tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 6 8.5 ns
tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA 8 11 ns
tCF Clock to internal feedback node delay time 4 5 7.5 ns
tINIT Delay from valid VDD to valid reset 50 50 ocs
tER Input to output disable3 12 15 ns
tEA Input to output valid 12 15 ns
tRP Input to register preset 12 15 ns
tRR Input to register reset 14 18 ns


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(1 Al Leat sink [ 3) With a 50x25x2mm Al heat sink
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