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Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
QMV760AZ5 NS      CQFP1420-100  929 

QMV760AZ5 Datasheet
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up tim e.
QMV760AZ5 Price

Angle Ta:25'C n
o -, rtcii.LiVe sensitivity


QMV760AZ5 on stock

VRRM 1 600 V
IFAV IDAVM IFSM Tc = 800C; sine 180 bridgeoutputcurrent; Te =800C; rectangular; d=1/3 TVJ = 250C; t = 10 ms; sine 50 Hz 23 65 250 A A A
Ptot Tc= 250C 65 W


The feedback configuration in Figure 6 is simply a resistive divider made up of Rl and R3 with Dl, R2, Cl and C2 rectifying, filtering and smoothing the primary winding voltage signal. The optocoupler therefore effectively adjusts the resistor divider ratio to control the DC voltage across Rl and therefore, the feedback current received by the LinkSwitch CONTROL pin.