QM80C31BH-B Datasheet POSTFACH 564 CH-8304 WALLISELLEN-ZURICH SWITZERLAND TELEX826 205 eltc ch (01) 830 00 01 OELTEC JH8TRUUEFITS INC'2ml lo U SA QM80C31BH-B Price (CR) that controls the operation. The A64E06161 is designed for reducing current consumption during hidden self refresh and operating through following mode: Deep Power Down (DPD) mode, Reduce Memory Size (RMS) mode, Partial Array Refresh (PAR) mode and Temperature Compensated refresh (TCR) mode. This A64E06161 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device. QM80C31BH-B on stock| SYMBOL | PIN | I/O | FUNCTION | | CPUCLK [0:1] | 52151 | OUT | Low skew(< 250ps) clock outputs for host frequencies such as CPU and Chipset. | | PD# | 22 | IN | Power Down mode when driven low. | | IOAPIC | 54 | OUT | Clock outputs synchronous with PCI clock and powered by VddA. | | SDRAM_F, SDRAM[O:11] | 38, 48,47,46, 44,43,42,40, 39,31, 30,27, 26 | OUT | SDRAM clock outputs. | | PCICLKO/'FSO | 1 1 | I/O | 3.3V 33MHz PCI clock during normal operation. Latched input for FSO at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=l). | | PCICLKl/ FSl# | 12 | I/O | Low skew(< 250ps) PCI clock outputs. Latched input for FSl at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). | | PCICLK2/'SEL24 48 | 12 | I/O | Low skew(< 250ps) PCI clock outputs. Latched input for SEL24_48 at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. | | PCICLK [ 3:7 ] | 15,16,17,19,20 | OUT | Low skew(< 250ps) PCI clock outputs. | | 3V66 [0:2] | 6,7,8 | OUT | 3.3V output clocks for the chipset. | | | | |
| | | | | LIMITS | | | SYMBOL | PARAMETER | TO | FROM | Min | Typi | Max | UNIT | | Access tlmez | | tAA tCE | | Output Output | Address Chip Enable | | | 50 30 | ns ns | | Dlsable timez | | tCD | | Output | Chip Disable | | | 30 | ns | | | | | | | | |
|
