QM40-8PL-PR Datasheet| UNIT | A | Ai max. | bp | c | D | E | e | e1 | HE | Lp | Q | V | W | | mm | 1 1 0 9 | 0 1 | 0 48 0 38 | 0 15 0 09 | 3 0 2 8 | 1 4 1 2 | 1 9 | 0 95 | 2 5 2 1 | 0 45 0 15 | 0 55 0 45 | 0 2 | 0 1 | | | | | | | | | | | | | | |
QM40-8PL-PR Price| Parameters | Values | Units | Conditions | | IF(AV, Max.AverageForward (PerLeg) | 40 | A | 50%duty cycle@Te=1110C,rectangularwave form | | Current (PerDevice) | 80 | | IFSM Max.PeakOneCycleNon-Repetitive | 1600 | A | 5ps Sineor3ljsRect.pulse | Followinc4:-any rated load conaition and with | | SurgeCurrent(PerLeg) | 500 | 10msSineor6msRect.pulse | rated VRRM applied | | EAS Non-RepetitiveAvalancheEnergy (PerLeg) | 50 | mJ | Tj=250C,l,xs=8Amps,L=1.5mH | | IAR RepetitiveAvalancheCurrent (PerLeg) | 8 | A | Current decaying linearly to zero in l psec Frequency limited by Tj max. VA = 1.5 x VR typical | | | | | |
QM40-8PL-PR on stock To drive the device from an external clock source, XTALl should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. | Parameter | Symbol | Values | Unit | | Collector-emitter voltage | E | 1 200 | V | | Collector-gate voltage RGE = 20 k] | VCGR | 1 200 | | Gate-emitter voltage | E | ±20 | | DC collector current Tc = 25 aC Tc = 100 0C | lc | 20 1 2 | A | | Pulsed collector current, tp = 1 ms Tc = 25 aC | /Cpuls | 40 | | Diode forward current Tc = 100 aC | F | tbd | | Pulsed diode current, tp = 1 ms Tc = 25 aC | /Fpuls | tbd | | Power dissipation Tc = 25 aC | Ptot | 1 25 | W | | Chip or operating temperature | Tj | -55+150 | aC | | Storage temperature | Tstg | -55+150 | | | | |
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