QM30-8PA-SP Datasheet| lTA | TQFP | | -400C to +1050C | QT60320D-AS | | |
QM30-8PA-SP Price These three terminal positive regulators are supplied in hermetically sealed packages. All protective features are designed into the circuit, including thermal shutdown, current-limiting, and safe-area control. With heat sinking, these devices can deliver up t0 1.5 amps of output current. The LCC-20 device is limited to .5 amps. The unit also features output voltages that can be fixed from l.2 volts t0 37 volts using external resistors. QM30-8PA-SP on stock| PIN | NAME | TYPE | DESCRIPTION | | 23 | STS1 0 | I | SONET STSl Mode Select - channel 0: This pin along with the DS3/E3_0 select pin configures the XRT71D04 either in E3, DS3 0r STS-1 mode. A table relating_to the setting of the pins is given below: STS-1 DS3/E3 XRT71D04 0perating Mode 0 0 DS3 (44.736 MHz) 0 1 E3 (34.368 MHz) 1 0 STS-1 (51.84 MHz) 1 1 E3 (34.368 MHz) This input pin is active only in the Hardware Mode. | | 24 | DS3/E3 0 | I | DS3/E3 Select Input - channel 0: See description pin 10. Internal 50 K Ohm pull-down resistor. | | 25 | DJA O/SCLK | I | Harware Mode Disable Jitter Attenuator Input - Channel 0: An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will be passed through without jitter attenuation. Host Mode Microprocessor Serial Interface Clock Signal: This signal will be used to (1) sample the data, on the SDI pin, on the rising edge of this signal. Additionally, during "Read" operations, the Microprocessor Serial Interface will update the SDO output on the falling edge of this signal. Internal 50 K Ohm pull-down resistor. | | 26 | MCLK 3 | I | Master Clock Input - channel 3: Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-20ppm. This clock must be continuous and jitter free with duty cycle between 30 t0 70%. It is permissible to use the EXCLK signal orSTSl clock. Internal 50 K Ohm pull-up resistor. | | 27 | GND | | Digital Ground | | 28 | RCLK 3 | I | Received Clock (Jittery) - channel 3: Clock input RCLK3 should be connected to the recovered clock. Internal 50 K Ohm pull-up resistor. | | 29 | RPOS 2 | I | Received Positive Data (Jittery) Input: - channel 2: Data that is input on this pin is sampled on either the rising or falling edge of RCLK depending on the setting of the RCLKES pin (pin 10). If RCLKES is "high", then RPOS will be sampled on the falling edge of RCLK. If RCLKES is "low", then RPOS will be sampled on the rising edge of RCLK. Internal 50 K Ohm pull-up resistor. | | 30 | RNEG 2 | I | Received Negative Data (Jittery) - channel 2: The inputjittery negative data is sampled either on the rising or falling edge of RCLK depending on the setting of RCLKES. If RCLKES is "high", then RNEG will be sampled on the falling edge of RCLK. If RCLKES is "low", then RPOS will be sampled on the rising edge of RCLK. This pin is typically tied to the "RNEG" output pin of the LIU. Internal 50 K Ohm pull-up resistor. | | 31 | VDD | | Digital Power Supply = 5V+5% or 3.3V+5% | | | | |
5.With register 08 at byte xOxxxxxx (C-Correction control is inhibited) then the C correction is inhibited, consequently the sawtooth has a linear shape. 6.lt is frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin 22, and with a constant ramp amplitude. 7.These parameters are not tested on each unit. They are measured during out internal qualification. 8.Refers to notes 4 & 5 from last section. 9.TH is the Horizontal period. 10.These parameters are not tested on each unit. They are measured during our internal qualification procedure which incudes characterization on batches comming from corners of our processes and also temperature char acterization. 11. See Figure 11 for explanation of reference phase. 12. See Figure 15. 13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single
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