QM10-32PAL-PR Datasheet| Name | I/O | Description | | AO, A1,A | Input- Synchronous | Address Inputs used to select one ofthe 128K address locations. Sampled at the rising edge of the CLK. A[i;ol are fed to the two-bit burst counter. | | BW[A:D] | Input- Synchronous | Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. | | WE | Input- Synchronous | Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. | | ADV/LD | Input- Synchronous | Advance/Loadlnput. Used to advance the on-chip address counterorload a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. | | CLK | Input-Clock | Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. | | CEi | Input- Synchronous | Chip Enable l Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. | | CE2 | Input- Synchronous | Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CEi and CE3 to select/deselect the device. | | CE3 | Input- Synchronous | Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CEi and CE2 to select/deselect the device. | | OE | Input- Asynchronous | Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the l/0 pins. When LOW, the l/0 pins are allowed to behave as outputs. When deasserted HIGH, l/0 pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. | | CEN | Input- Synchronous | Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. | | | |
QM10-32PAL-PR Price (7) The LEDs described in this brochure are intended to be used for ordinary electronic equipment (Such as office equipment, communications equipment, on the applications in which exceptional quality and reliability are required, particularly when the failure or malfunction of the LEDs may directly jeopardize life or health (such as for airplanes, aerospace, submersible repeaters, nuclear reactor control systems, automobiles, traffic control equipment, life support systems and safety devices) QM10-32PAL-PR on stock DESCRIPTION The P23128 CPLD (Complex Programmable Logic Device) is the third in a family of Fast Zero Power (FZPT') CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZPTM design technique, the P23128 0ffers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than l OOccA at standby without the need for 'turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD - 70% lower at 50MHz. These devices are the first TotaICMOSTM PLDs, as they use both a CMOS process technology and the patented full CMOS FZPTM design technique. For 5V applications, Philips also offers the high speed P25128 CPLD that offers these features in a full 5V implementation. | Parameters | SD203N/R | Units | | IF[AV, | 200 | A | | @ Te | 85 | oc | | IF(RMS, | 314 | A | | IFSM @50Hz | 4990 | A | | @ 60Hz | 5230 | A | | 12t @50Hz | 125 | KA2S | | @ 60Hz | 114 | KA2S | | VRRM range | 400 t0 2500 | V | | trange | 1.0 t0 2.0 | US | | @T | 25 | oc | | Tj | - 40 t0 125 | oc | | | |
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