Start Up Until the voltage on the Vcci supply pin exceeds the 3.9V monitor threshold, the soft start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up t0 1V by the comparator clamp. When the Vcci pin exceeds the monitor threshold, the Gate output is activated, and the soft start capacitor begins charging. The Gate output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the lV level, the pulse is terminat- ed. The Gate pin drives low for the duration of the extend- ed off time. This time is set by the time out timer and is
QLCBM61A-068N Price| | | | | | | I | | |
| 1s i | | | 7 ) | 7> | l | }7 | | 100rns i |
| | | | | | | | 1 <imfi . ] |
| | | | | | | 100us |
| | | | | | | |
| | | | | | | | |
QLCBM61A-068N on stock| Pin Name | Function |
| CS | Chip Select |
| SCK | Serial Clock |
| sI | Serial Input |
| SO | Serial Output |
| WP | Hardware Page Write Protect Pin |
| RESET | Chip Reset |
| RDY/BUSY | Ready/Busy |
| |
