QL4016-0PL84C Datasheet| Option | Conditions and notes | | I Output high at reset | The four bits of ports 0, 1, 4, 5, or 8 are set in a group | | I Output low at reset | The four bits of ports 0, 1, 4, 5, or 8 are set in a group | | |
QL4016-0PL84C Price The receiver design features clamp circuitry to cause a defined output state if both the inverting and non-inverting inputs are left open; in this case the Q output goes low, while the Q* output goes high. This feature makes the device ideal for twisted pair applications. QL4016-0PL84C on stock| | | (1) Tc=Ta (2) With a 50X50X2mm | | | | Al heat smk (3) With a 50 X 25 X2mm | | (1) | | Al heat smk (4) WithouL heat sink | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J2) | | | | | | | | | (3) | | | | | j | | | | (4) | | | | | | | | | | | | | | | | | | | | | | | | |
| Symbol | Parameter | Condition | Min | Typ | Max | Units | | fMAX | Maximum Operating Frequency | Clock | 1.5 | 2.0 | | GHz | | tpd | Differential Propagation Delay In-to-Q | 100rTiV < VIN < 200rrlV(8) | 440 | 625 | 840 | ps | | In-to-Q | 200r71V < VIN < 800rrlV(8) | 390 | 550 | 770 | ps | | SEL-to-Q | RPE enabled, see Timing Diagram | | | 17 | cycles | | SEL-to-Q | RPE disabled (VSEL = Vcc/2) | 530 | | 880 | ps | | tpd Tempco | Differential Propagation Delay Temperature Coefficient | | | 410 | | fs/oC | | LSKEW | Output-to-Output Skew | Note 9 | | 5 | 20 | ps | | Part-to-Part Skew | Note 10 | | | 200 | ps | | tjITTER | Clock Random Jitter | Note 11 | | | 1 | psRMS | | Cycle-to-Cycle Jitter | Note 12 | | | 1 | ps RMS | | Total Jitter | Note 13 | | | 10 | psPP | | Crosstalk-Induced Jitter | Note 14 | | | 0.7 | psRMS | | tr tf | Output Rise/Fall Time (20% t0 80%) | At full output swing. | 30 | | 80 | ps | | | | | | | |
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