PC180CH204JAD Datasheet| Parameter | Symbol | Conditions | Min | Typ | Max | Unit | | Collector-emitter voltage | 2SB0938 | VCEO | Ic = -30 rriA. IB = 0 | -60 | | | V | | (Base open) | 2SB0938A | -80 | | | | Base-emitter voltage | VBE | VCE = -3 V,IC = -3 A | | | -2.5 | V | | Collector-base cutoff' | 2SB0938 | ICBO | VCB = -60 V,IE = 0 | | | -200 | LLA | | current (Emitter open) | 2SB0938A | VCB = -80 V,IE = 0 | | | -200 | | Collector-emitter cutoff' | 2SB0938 | ICEO | VCE = -30 V,IB = 0 | | | -500 | LLA | | current (Base open) | 2SB0938A | VCE = -40 V,IB = 0 | | | -500 | | Emitter-base cutoff current (Collector open) | IEBO | VEB = -5 V,IC = 0 | | | 2 | mA | | Forward current transf'er ratio | hFEl | VCE = -3 V, IC = -0.5 A | 1 000 | | | | | hFE2 8 | VCE = -3 V,IC = -3 A | 2000 | | 10000 | | Collector-emitter saturation voltage | VCE(sat) | IC = -3 A,IB = -12 mA | | | 2 | V | | Ic = -5 A,IB = -20 mA | | | -4 | | Transition frequency | fr | VCE = -10 V,IC = -0.5 A, f= 1 MHz | | 15 | | MHz | | rurn-on time | ton | IC = -3 A, | | 0 3 | | Lis | | Storage time | tstg | IBl = -12 mA,IB2 = 12 mA | | 2 | | 11s | | Fall time | tr | VCc = -50 V | | 0 5 | | !1s | | | | | | | | |
PC180CH204JAD Price| Symbol | Parameter | Value | Unit | | Rtr, O-a) | Junction-to-ambient | 80 | oC/W | | | | |
PC180CH204JAD on stock| | | 2.5V RANGE LIMITS | 3.3V RANGE LIMITS | | | SYMBOL | PARAMETER | MIN | MAX | MIN | MAX | UNIT | | Vcc | DC supply voltage | 2 3 | 2 7 | 3.0 | 3.6 | V | | VI | Input voltage | 0 | 5 5 | O | 5.5 | V | | VIH | High-Ievel input voltage | 1 7 | | 2.0 | | V | | VIL | Input voltage | | 0 7 | | 0.8 | V | | IOH | High-Ievel output current | | -8 | | -32 | mA | | | Low-Ievel output current | | 8 | | 32 | | | IOL | Low-Ievel output current; current duty cycle " 50%; f > 1 kHz | | 24 | | 64 | mA | | | Input transition rise or fall rate; Outputs enabled | | 10 | | 10 | nsN | | Tamb | Operating free-air temperature range | -40 | +85 | -40 | +85 | YC | | | | | | | |
| Errata Number | Document UDdate | Applies to Mask | | ED37 | Description (added 4/19/99): In paragraph 6.1.1.11 0n page 6-12 0f the 301 User's Manual, there is an error, as follows: "HIRQ_ is asserted by the HI32 when a host interrupt request (recieve and/or transmit) is generated in the HI32" Workaround/correction: Should be: "HIRQ_ is asserted by the HI32 when a host interrupt request (receive and/or transmit) is generated in the HI32 (as described in paragraphs 6.2.1.1, 6.2.1.1 and 6.2.1.4)." | 2K30A | | ED38 | Description (added 7/ 14/ 99): If Port A is used for external accesses, the BAT bits in the AAR3-0 registers must be initialized to the SRAM access typ e (i.e. BAT = 01) or to the DRAM access type (i.e. BAT = 10). To ensure prop er op eration ofPort A, this initialization must occur even for an AAR register that is not used during any Port A access. N ote that at reset, the BAT bits are initialized t0 00. Pertains to: DS P56300 Fam ily Manual, Port A Chapter (Chapter 9 in Revision 2), description ofthe BAT[1 -0] bits in the AAR3 - AARO registers. Also pertains to the core chapter in device-specific user's manuals that include a description of the AAR3 - AARO registers with bit definitions (usually Chapter 4). | 2K30A | | | |
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