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PC16S7VP4S47KA Datasheet

These devices feature the ability to clamp dangerous high voltage short term transients such as produced by directed or radiated electro-static-discharge phenomena before entering sensitive component regions of a circuit desig n. They are small economicaltransient voltage suppressors targeted primarily for short term transients below a few microseconds while still achieving significant peak-pulse-power capability as seen in Figure #1.
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In this mode, full equalization is applied to the input p signal irrespective of amplitude. Additionally, there are four No-Connect pins (2,3,7,8) which also mustt be left unconnected for normal operation. 3) No Equalization ('EQSEL high)
PC16S7VP4S47KA on stock

	f U					J L
	VOlmA[y)	AC rms[V)	DC (VJ	Vi^ (vJ	(w)	(J)	[AJ	@l kHz (pF)
ENC220D-05B	22(2024)	14	18	48		0 4		1200
ENC270D-05B	27 (2430)	17	22	60		0 5		1100
ENC330D-05B	33 (30-36)	20	26	73		0 6		1000
ENC390D-05B	39 (3543)	25	31	86	0 01	0 8	125	800
ENC470D-05B	47 (4252)	30	38	104		1 0		700
ENC560D-05B	56(5062)	35	45	123		1.0		600
ENC680D-05B	68 (6175)	40	56	150		1 2		500

PARAMETER	TEST CONDITIONS	MIN TYP MAX	UNIT
CONTROL SIGNALS: LOW_PWR, SCLK, SDAT (Input
VIH High-Ievel input voltage	IIH = 20 pA (i}	2 Vce	V
VIL Low-Ievel input voltage	I= 10 pA	0 0 8	V
IIB Input bias current		0 01 1 0	UA
CONTROL SIGNALS: PB_ONOFF, HOT_RESET, BATT_COVER
VIH High-Ievel input voltage	IIH = 20 pA(i)	0.8 Vcc 6	V
VIL Low-Ievel input voltage	l= 10UA	0 0 4	V
R(pb_ono) Pulldown resistor at PB_ONOFF		1000	kI
Pullup resistor at HOT_RESET, R(hot_reset) connected to VCC		1000	kI
R(ba"_cover} Pulldown resistor at BATT_COVER		2000	kl
t(glitch) De-glitch time at all 3 pins		38 56 77	ms
Delay after t(glitcri} (PWRFAIL goes low) t(batt_cover} before supplies are disabled when BATT COVER goes low.		1 68 2 4 3 2	ms
CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON,INT, SDAT (output)
VOH High-Ievel output voltage		6	V
VOL Low-Ievel output voltage	l--= 10 mA	0 0 3	V
td(mpu_nreset) Duration oflow pulse at MPU_RESET		100	US
td(nrespwron) Duration oflow pulse at RESPWRON	TPOR=O	80 100 120
after VMAIN is in regulation	TPOR=1	800 1000 1200	ms
Time between UVLO going active td(uvlo) PW~AFL going low) and supplies be- ing disabled		1 68 2 4 3 2	ms
Time between chip overtemperature td(overtemp) condition being recognized (PWRFAIL going low) and supplies being disabled		1 68 2 4 3 2	ms
SUPPLY PIN: VCC
I(o} Operating quiescent current	Vl = 3.6 V, current into Main + Core + Vcc	70	UA
IO(SD) Shutdown supply current	VI = 3.6 V, BATT_COVER = GND, Current into Main + Core + Vcc	15 25	UA
VMAIN STEP-DOWN CONVERTER
Vi Input voltage range		2 5 6 0	V
la Maximum output current		1000	mA
IO(SD) Shutdown supply current	BATT COVER = GND	0 1 1	UA
rOS(on) P-channel MOSFET on-resistance	VI(MAIN) = VGS = 3.6 V	110 210	m

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