PC1602LRMQSOC PC1602LRMQSOC PC1602LRMQSOC Datasheet The SY10/100EL34/L are low skew x/2, x/4, x/8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC- coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a O.OlccF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up t0 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. PC1602LRMQSOC PC1602LRMQSOC PC1602LRMQSOC Price| MNEMONIC | DIP PIN NO. | TYPE | NAME AND FUNCTION | | VSS Vcc P1.O-P1.2 P3.O-P3.7 RST X1 X2 AVcc 1 AVSS1 ZIN YIN XIN XYZRAMP DECOUPLE VREG XYDACBIAS XYSOURCE ZDAC XYDAC | 8 22 21, 23, 24 24 23 1-4, 25-28 3 1 4 2 5 7 6 14 13 9 10 11 12 15 16 17 18 19 20 | I I I/O I 0 1/0 I I I I I I o I I I I I 0 0 o 0 0 o 0 | Circuit Ground Potential. Supply voltage during normal, idle, and power-down operation. Port l: Port l is a 3-bit bidirectional l/0 port with internal pull-ups on Pl.0 and Pl.1. Port l pins that have ls written to them can be used as inputs. As inputs, port l pins that are externally pulled low will source current because of the internal pull-ups (P1 .0, P1.1 ). (See DC Electrical Characteristics: IlL). Port l also serves the special function features listed below (Note: P1.0 does not have the strong pullup that is on for 2 0scillator periods.): INTO (P1.0): External interrupt 0. CEX (P1.1): PCA clock output. Port 3: Port 3 is an 8-bit bidirectional l/0 port with internal pull-ups. Port 3 pins that have ls written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IlL) (Note: P3.5 does not have the strong pullup that is on for 2 0scillator periods.) Port 3 also serves the special function as listed below: ECI (P3.6): External PCA clock input. RxD/TO (P3.4): Serial port receiver data input. Timer o external clock input. INTl: External interrupt l. TxD/T1 (P3.5): Serial port transmitter data. Timer l external clock input. Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. (NOTE: The TPM754 does not have an internal reset resistor.) Crystal l: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. Analog supply voltage and reference input. Analog supply and reference ground. ZIN: Input to analog multiplexer. YIN: Input to analog multiplexer. XIN: Input to analog multiplexer. XYZRAMP: Provides a low impedance pulldown to Vss under S/W control. DECOUPLE: Output from regulated supply for connection of decoupling capacitors. VREG: Provides regulated analog supply output. XYDACBIAS: Provides source voltage for bias of external circuitry. XYSOURCE: Provides source voltage from regulated analog supply. ZDAC: Switchable output from the internal DAC. XYDAC: Non-switchable output from the internal DAC. | | | | |
| Symbol | Characteristics | | All | Units | Remark | | RthJc | Junction-to-Case | MAX | 3.0 | K/W | | | Rthcs | Casa-to-Sink | TYP | 1.7 | K/W | Mounting surface flat, smooth and greased | | RthjA | Junction-to-Ambient | MAX | 110 | ww | Free Air Operation | | | | | | |
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