| Symbol | Name and Function |
| READY | Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. |
| HSI | Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSl.2 and HSl.3. Two of them (HSl.2 and HSl.3) are shared with the HSO Unit. |
| HSO | Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HS0.2, HSl.3, HS0.4 and HS0.5. Two of them (HS0.4 and HS0.5) are shared with the HSI Unit. |
| Port O | 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. |
| Port l | 8-bit quasi-bidirectional I/O port. |
| Port 2 | 8-bit multi-functional port. All of its pins are shared with other functions in the 87C1 96KD. |
| Ports 3 and 4 | 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus. |
| HOLD | Bus Hold input requesting control of the bus. |
| HLDA | Bus Hold acknowledge output indicating release of the bus. |
| BREQ | Bus Request output activated when the bus controller has a pending external memory cycle. |
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