| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
PC11438 PC11438 PC11438 Datasheet
PC11438 PC11438 PC11438 Price BA6162 / F: Vs = 4.2Vtyp. when Vcc drops, and Vs + O.lVtyp. when Vcc rises), the Reset signal (Low) and the CS signal (CS-Low, CSB-High) are output by the logic output function, and the SRAM (or other memory device) is switched to backup mode. lf the power supply Vcc drops further and goes below the switching voltage (BA6129AF and BA6162 / F: VB = 3.3Vtyp. when Vcc drops, VB + O.lVtyp. when Vcc rises), the SBD develops a forward bias because the PNP power transistor is off. The power supply output Vo switches from the power supply Vcc to the battery power supply (VBAT). When the normal power supply Vcc rises, the above process is reversed. PC11438 PC11438 PC11438 on stock Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use. Parameter Block 2, Main Memory Block l, and Main Mem- ory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are tw0 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and repro- grammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can con- vert "O"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. |
