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PC10EP58D PC10EP58D PC10EP58D Datasheet

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
PC10EP58D PC10EP58D PC10EP58D on stock

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PARAMETER	TEST CONDITIONS	MIN TYP MAX	UNIT
CONTROL SIGNALS: LOW_PWR, SCLK, SDAT (Input
VIH High-Ievel input voltage	IIH = 20 pA (i}	2 Vce	V
VIL Low-Ievel input voltage	I= 10 pA	0 0 8	V
IIB Input bias current		0 01 1 0	UA
CONTROL SIGNALS: PB_ONOFF, HOT_RESET, BATT_COVER
VIH High-Ievel input voltage	IIH = 20 pA(i)	0.8 Vcc 6	V
VIL Low-Ievel input voltage	l= 10UA	0 0 4	V
R(pb_ono) Pulldown resistor at PB_ONOFF		1000	kI
Pullup resistor at HOT_RESET, R(hot_reset) connected to VCC		1000	kI
R(ba"_cover} Pulldown resistor at BATT_COVER		2000	kl
t(glitch) De-glitch time at all 3 pins		38 56 77	ms
Delay after t(glitcri} (PWRFAIL goes low) t(batt_cover} before supplies are disabled when BATT COVER goes low.		1 68 2 4 3 2	ms
CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON,INT, SDAT (output)
VOH High-Ievel output voltage		6	V
VOL Low-Ievel output voltage	l--= 10 mA	0 0 3	V
td(mpu_nreset) Duration oflow pulse at MPU_RESET		100	US
td(nrespwron) Duration oflow pulse at RESPWRON	TPOR=O	80 100 120
after VMAIN is in regulation	TPOR=1	800 1000 1200	ms
Time between UVLO going active td(uvlo) PW~AFL going low) and supplies be- ing disabled		1 68 2 4 3 2	ms
Time between chip overtemperature td(overtemp) condition being recognized (PWRFAIL going low) and supplies being disabled		1 68 2 4 3 2	ms
SUPPLY PIN: VCC
I(o} Operating quiescent current	Vl = 3.6 V, current into Main + Core + Vcc	70	UA
IO(SD) Shutdown supply current	VI = 3.6 V, BATT_COVER = GND, Current into Main + Core + Vcc	15 25	UA
VMAIN STEP-DOWN CONVERTER
Vi Input voltage range		2 5 6 0	V
la Maximum output current		1000	mA
IO(SD) Shutdown supply current	BATT COVER = GND	0 1 1	UA
rOS(on) P-channel MOSFET on-resistance	VI(MAIN) = VGS = 3.6 V	110 210	m

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