| NAME | DESCRIPTION | SFR Address | BIT FUNCTIONS AND ADDRESSES MSB LSB | Reset Value |
| | | | 3F7 3F6 3F5 3F4 3F3 3F2 3F1 3FO | |
| ADCON#* | A/D control register | 43E | | | | | ADRES | ADMOD | ADSST | ADINT | OOh |
| 3FF 3FE 3FD 3FC 3FB 3FA 3F9 3F8 |
| ADCS#* | A/D channel select register | 43F | ADCS7 | ADCS6 | ADCS5 | ADCS4 | ADCS3 | ADCS2 | ADCS1 | ADCSO | OOh |
| ADCFG# | A/D timing configuration | 489 | | | | | A/D Timing Configura | on | OFh |
| ADRSHO# ADRSHl# ADRSH2# ADRSH3# ADRSH4# ADRSH5# ADRSH6# ADRSH7# ADRSL# | A/D high byte result, channel 0 A/D high byte result, channel 1 A/D high byte result, channel 2 A/D high byte result, channel 3 A/D high byte result, channel 4 A/D high byte result, channel 5 A/D high byte result, channel 6 A/D high byte result, channel 7 Two LSBs of 10-bit A/D result | 4BO 481 482 483 484 485 486 487 488 | | xx xx xx xx xx xx xx xx xx |
| BCR# | Bus configuration register | 46A | | | CLKD | WAITD | BUSD | BC2 | BC1 | BCO | Note 1 |
| BTRH | Bus timing register high byte | 469 | DW1 | DWO | DWA1 | DWAO | DR1 | DRO | DRA1 | DRAO | FFh |
| BTRL | Bus timing register low byte | 468 | WM1 | WMO | ALEW | | CR1 | CRO | CRA1 | CRAO | EFh |
| 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2DO |
| CCON#* | PCA counter control | 41A | CF | CR | | CCF4 | CCF3 | CCF2 | CCF1 | CCFO | OOh |
| CMOD# | PCA mode control | 490 | CIDL | WDTE | | | | CPS1 | CPSO | ECF | OOh |
| CH# CL# | PCA counter high byte PCA counter low byte | 48B 48A | | OOh OOh |
| CCAPMO# | PCA module o mode | 491 | | ECOMO | CAPPO | CAPNO | MATO | TOGO | PWMO | ECCFO | OOh |
| CCAPMl# | PCA module l mode | 492 | | ECOM1 | CAPP1 | CAPN1 | MAT1 | TOG1 | PWM1 | ECCF1 | OOh |
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