| JEOEC TYPE FIUMBER (NotP l) | ZEFJER VOLTAGE (vz) ihIOTE 4) | TEST CURREbiT | MAXIMUM OYNAMJC 1MPEOANCE (Zir r IZT) (Note 2) | MAXIMUM REVERSE CUr?RENT [IR r VR) | TEST VOLTAGE | MAXIMUM REGULATOR CURRENT (im) TA - 50qc | MAXIMUM KNEE MPEDANCE Zzk izx) (Note 2) | TEST CUF?RENT { izk) | MAXIMUM (SURCE) CURRENT [is) (Note 3) |
| VOLTS | mA | OHMS | nA | VOLTS | mA | OHMS | mA | |
| 1N4728A 1H4729A 1N4730A 1N4731A | 3 3 3 6 3 9 4 3 | 76 69 64 58 | 10 10 | 1 00 1 00 50 1 0 | 1 | 276 252 234 217 | 40 40 40 40 | 1 0 1 0 1 0 1 0 | 13 8 12 6 119 10 7 |
| 1N4732A 1N4733A 1N4734A 1N4735A | 4 7 5.1 5 6 6 2 | 53 49 45 41 | 2 | 10 10 10 10 | 3 | 193 17 8 16 2 14 6 | 50 55 60 70 | 1 0 1 0 1 0 1 0 | 97 89 81 73 |
| 1N4736A 1N4737A 4738A liq4739A | 6 8 7 5 8 2 9 1 | 37 34 31 28 | 3 5 4 0 4 5 5 0 | 10 10 10 10 | 7 | 13 3 121 11 10 | 70 70 70 70 | 1 0 0 5 0 5 0 5 | 66 605 55 50 |
| 1F14740A 4741A 1N4742A 1N4743A | 10 11 12 13 | 25 23 21 19 | 10 | 10 | 7 6 8 4 9.1 9 9 | 91 83 76 69 | 700 70 ;r0 70 | 0.25 0.25 0.25 0.25 | 454 414 38 344 |
| 1H4744A 1FJ4745A 1N4746A 1N4747A | 15 16 18 20 | 17 15 5 14 12 5 | 14 16 20 22 | 5 | 11.4 12.2 13.7 15.2 | 61 57 50 45 | 70 70 75 75 | 0.25 0.25 0.25 0.25 | 304 285 25 225 |
| 1H4748A 1N4749A 1N4750A 1N4751ll | 22 24 27 30 | 11 5 10 5 9 5 8 5 | 23 25 35 40 | 5 | 16.7 18.2 20.6 22.8 | 41 38 34 30 | 75 75 75 10 0 | 0.25 0.25 0.25 0.25 | 205 19 17 15 |
| 4752A 1H4753A 1N4754A 1N4755A | 33 36 39 43 | 7 5 7 0 6 5 6 0 | 45 50 60 70 | 5 | 25.1 27.4 29.7 32.7 | 27 25 23 22 | 10 0 10 0 10 0 15 0 | 0.25 0.25 0.25 0.25 | 13 5 12 5 115 11 |
| 1tl4756A ihl4757A ihl4758A 1N4759A | 47 51 56 62 | 5 5 5 0 4 5 4 0 | 80 95 110 125 | 5 | 35.8 38 8 42.6 47.1 | 19 18 16 14 | 150 150 200 200 | 0.25 0.25 0.25 0.25 | 95 90 80 70 |
| 1N4760A 1H4761A 1N4762A 1H4763A | 68 75 82 91 | 3 7 3 3 3 0 2 8 | 15 17 5 20 25 | 5 | 51.7 56. 62 2 69 2 | 13 12 11 10 | 200 200 300 300 | 0.25 0 25 0.25 0.25 | 65 60 55 50 |
| 1N4764A | 100 | 2 5 | 350 | 5 | 76 0 | 9 | 3000 | 0 25 | 45 |
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NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CEl and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CEl or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5.lfthe CEl low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. Dou r is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CEl is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. Tcw iS measured from the later of CEl going low or CE2 going high to the end of write.
| CHARACTERISTIC | SYMBOL | MAX | UNIT |
| Thermal Resistance, Channel to Case | Rth (ch-c) | 2.78 | oC /W |
| Thermal Resistance, Channel to Ambient | Rth (ch-a) | 62.5 | oC /W |
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