- Direct connection t0 68xxx family and mappable to non-68xxx processors Complete master/slave capability - Supports read, write, write posting, and block trans- fers -Accommodates VMEbu' ng requirements with internal digital delay l:e t(im2_cglock granularity) - Programmable metastability delay - Programmable data acquisition delays - Provides timeout timers for local bus and VMEbus transactions Interleaved block transfers over VMEbus -Acts as DMA master on local bus
PC07E1210S Price| ) | ( ) | < |
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| tDW | tDH-h |
| High-Z 1 ]7icx | V N Valid Data>}High-Z |
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PC07E1210S on stock| Characteristic | Symbol | Test Conditions | Min | Typ | Max | Unit |
| DTMF GAIN | Gv (MF) | RTX = 68KC2 (MUTE = H) | 23 5 | 25 5 | 27 5 | dB |
| DTMF Input Impedance | Zl (MF) | | | 20 7 | | KQ |
| | VIH (MUTE) | | 1 5 | | Vcc | V |
| MUTE Input Voltage | VIL (MUTE) | | | | 0 8 |
| TX Gain variation range by AGC | AGTXA | RAGC = 180KC) IL = 15 ~ 80mA | | -6 | | dB |
| RX Gain variation range by AGC | AGRXA | RAGC = 180KC) IL = 15 ~ 80mA | | -6 | | dB |
| TX Noise Output Voltage (Psophometric weighted) | VTNO | | | -72 | | dBmp |
| RX Noise Output Voltage (Psophometric weighted) | VRNO | | | 50 | | uV |
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| 7D.C. OPER~T | 0N | | | | | | |
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