PC01T06 Datasheet| TERMINAL | | | | NAME | NO | lO | DESCRIPTION | | GQE | RCP | | ENABLE | A5 | 24 | I | Device enable. When this terminal is held low, the device is placed in power-down mode. Only the signal detect circuit on the serial receive pair is active. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation. | | GND | A1, J1, D3, E3, F3, G3, C4, D4, E4, F4, G4, A9, J9 | 5, 13, 18, 28, 33, 43 | | Digital logic ground. Provides a ground for the logic circuits and digital l/0 buffers. | | GNDA | H4H6 | 52, 58, 61 | | Analog ground. GNDAprovides a ground reference forthe high-speed analog circuits, RXand TX. | | LCKREFN | B5 | 25 | I | Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to TXCLK. This places the device in a transmit only mode since the receiver is not tracking the data. When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RXCLK and RKLSB, RKMSB are in a high-impedance state. When LCKREFN is deasserted high, the receiver is locked to the received data stream. | | LOOPEN | B6 | 21 | I | Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a hig h-impedance state du ring the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. | | PRE | J5 | 56 | I | Preemphasis control. Selects the amount of preemphasis to be added to the high speed serial output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis is added. | | PRBSEN | A4 | 26 | l | PRBS testenable.When asserted high results of pseudo random bit stream (PRBS) tests can be monitored on the RKLSB terminal. A high on RKLSB indicates that valid PRBS is being received. | | RKLSB | A3 | 29 | O | K-Code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was received and is indicated by data bits RXDO-RXD7. When RKLSB is asserted low an 8-bit/10-bit D code is received and is presented on data bits RXDO-RXD7. When PRBSEN is asserted high this pin is used to indicate status of the PRBS test results (high = pass). | | RKMSB | B3 | 30 | 0 | K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is indicated by data bits RXD8 -RXD15. When RKMSB is asserted low an 8-bit/10-bit D code was received and is presented on data bits RXD8 - RXD15. If the differential signal on RXN and RXP drops below 200 mV, then RXD [0:15], RKLSB, and RKMSB are all asserted high. | | RXCLK RX CLK | E2 | 41 | O | Recovered clock. Output clock that is synchronized to RXD [0..9], RKLSB, and RKMSB. RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on reset. | | | | | |
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EXTVcc (Pin 30): External Power Input to an Internal Switch Connected to INTVcc. This switch closes and supplies Vcc power, bypassing the internallow dropout regulator, when- ever EXTVcc is higher than 4.7V. See EXTVcc connection in Applications section. Do not exceed 7V on this pin.
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