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PC-20-60B13 Datasheet

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PC-20-60B13 Price

Pin Name	Pin	Type	Description
TAl+, TAl-	48, 49	LVDS OUT
TBl+, TBl-	46, 47	LVDS OUT
TCl+, TCl-	43, 44	LVDS OUT	The lst Link. The lst pixel output data when Dual Link.
TDl+, TDl-	39, 40	LVDS OUT	The lst Link. The lst pixel output data when Dual Link.
TCLKl+, TCLKl-	41, 42	LVDS OUT	LVDS Clock Out for lst Link.
TA2+, TA2-	36, 37	LVDS OUT
TB2+, TB2-	34, 35	LVDS OUT
TC2+, TC2-	31, 32	LVDS OUT	The 2nd Link. These pins are disabled when Single Link.
TD2+, TD2-	27, 28	LVDS OUT	The 2nd Link. These pins are disabled when Single Link.
TCLK2+, TCLK2-	29, 30	LVDS OUT	LVDS Clock Out for 2nd Link.
R17Rl0	60, 59, 58, 57, 54, 53, 52, 51	IN
G17Gl0	68, 67, 66, 65, 64, 63, 62, 61	IN	The lst Pixel Data Inputs.
B17Bl0	78, 77, 76, 75, 74, 73, 70, 69	IN	The lst Pixel Data Inputs.
R27R20	86, 85, 84, 83, 82, 81, 80, 79	IN
G27G20	96, 95, 94, 93, 92, 91, 90, 89	IN	The 2nd Pixel Data Inputs.
B27B20	6, 5, 2, 1, 100, 99, 98, 97	IN	The 2nd Pixel Data Inputs.
DE	9	IN	Data Enable Input.
VSYNC	8	IN	Vsync Input.
HSYNC	7	IN	Hsync Input.
CLKIN	10	IN	Clock Input.
TESTl, TEST5	13, 22	OUT	Test Pins.
TEST3, TEST4	20, 21	IN	Test Pins, must be L for normal operation.
TEST2	14	IN	Test Pins, must be H for normal operation.
/PDrN	19	IN	H: Normal operation, L: Power down (all outputs are Hi-Z)
6/8	18	IN	6bit/8bit color select. H: 6bit (TDx+/- are GND), 1: 8bit.
OE	17	IN	Output enable. H: Output enable, L: Output disable (all outputs are Hi-Z)
			Pixel Data Mode.
				MODE1	MODEO	Mode
MODEl, MODEO	15, 16	IN		L	L	Dual Link (Dual-in/Dual-out)
				L	H	Single Link (Dual-in/Single-out)
				H	H	Single Link (Single-in/Single-out)
RS	12	IN	LVDS swing range select. H: Normal range, L: Reduced range.

PC-20-60B13 on stock

PNP Silicon Digital Transistor Preliminary data . Switching circuit, inverter, interface circuit, driver circuit . Two ( galvanic) internal isolated Transistors with good matching in one package . Built in bias resistor (Ri = 4.7kQ)

Symmetrical output impedance High noise immunity ESD protection: x HBM EIA/JESD22-A114-A exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V x CDM EIA/JESD22-C101 exceeds 1 000 V. Low power dissipation Balanced propagation delays SOT505-2 and SOT765-1 package Specified from -40 IC to +85 IC and from -40 IC to +125 IC

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