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PC-12-350B6 Datasheet

Fast Programming Algorithm Fast Programming Algorithm rapidly programs M27512 EPROMs using an efficient and reliable method suited to the production programming en- vironment. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flowchart of the M27512 Fast Programming Algorithm is shown in Figure 8.
PC-12-350B6 Price

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PARAMETER	SYMBOL	TEST CONDITIONS		MIN	TYP	MAX	UNITS
Drain to Source Breakdown Voltage	BVDSS	ID = 250D:A, VGS = OV (Figure 11)		60			V
Gate to Source Threshold Voltage	VGS(TH)	VGS = VDS, ID = 250D:A (Figure 10)		1		2	V
Zero Gate Voltage Drain Current	IDSS	VDS = 60V, VGS = OV				1	o:A
Zero Gate Voltage Drain Current	IDSS	VDS = 60V, VGS = OV, TA = 1500C				50
Gate to Source Leakage Current	IGSS	VGS= +10V				10
Drain to Source On Resistance	rDS(ON)	ID = 2.OA, VGS = 5V (Figure 9)			0.110	0 150	l
Turn-On Time	tON	VDD = 30V, ID -' 2.OA,				120	ns
Turn-On Delay Time	'd(ON)	RL = 151 , VGS = 5V, RGS = sl			10		ns
Rise Time	tr	(Figure 12)			70		ns
Turn-Off Delay Time	td(OFF)				30		ns
Fall Time	tf				25		ns
Turn-Off Time	tOFF					85	ns
Total Gate Charge	Qg(TOT)	VGS = OV t0 10V	VDD = 30V,		28	35	nC
Gate Charge at 10V	Qg(5)	VGS= OV t0 5V	ID - 2.OA, RL = isl		15	18	nC
Threshold Gate Charge	Qg(TH)	VGS= OV t0 1V	lg(REF) = 1.OmA (Figure 15)		1 0	1.2	nC
Input Capacitance	CISS	VDS = 25V, VGS = OV,			850		pF
Output Capacitance	bOSS	f=lMHz (Figure 12)			170		pF
Reverse Transfer Capacitance	LRSS	f=lMHz (Figure 12)			100		pF
Thermal Resistance Junction to Ambient	ROJA	Pad Area = 0.171 in2 (see note 2)				110	oc/w
		Pad Area = 0.068 in2				128	oC/W
		Pad Area = 0.026 in2				147	oc/w

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