| PAD | Name | I/O | Description |
| 65 | JAMO | O | Forced Jam Out. Active High. The OR'd forced jam signals controlled by |
| CMOS | Carrier Integrity Monitor of each port. If collision occurs inside the XRC lI (exclude JAMI), this pin is also asserted. |
| 66 | JAMI | l | Forced Jam Input. Active High. Asserted by external arbitor, and XRCII will |
| TTL | generate JAM patterns to all its ports whenever this signal is validate more than 40 ns. This signal is filtered by LSCLK for 40ns internally. |
| 68 | EDENL | l | Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC lI |
| Sche | will not drive data onto EDAT until this pin is asserted. Assertion time less than 40ns will not be recognized by XRC lI. |
| 63-59 | EDAT[4:0] | I/O | Expansion Data. Bidirectional 5 bit-wide data. By default, EDAT is an input. |
| TTL | An external arbitor coordinates multiple devices on EDAT. |
| 64 | EPCLK | I/O | Expansion port Data Clock. This clock will be outputed by XRCII along with |
| TTL | the EDAT[4:0]. Another module ofXRCII should use this signal as expansion port data input clock. |
| 70 | ANYACT | O | Any Activity. Active High. When XRCII tries to release data onto EDAT, this |
| CMOS | pin will be asserted by XRC II. |
| 67 | EDCRS | l | Expansion Data Carrier Sense. When this pin is asserted, XRC II will |
| Sche | recognize that there is activity on expansion port data bus EDAT and perform corresponding activity within XRCII itself. |
| 71 | EDACT | O | Expansion Data Activity. When XRCII detects that EDENL is asserted by |
| CMOS | external arbitor, it will assert EDACT high. System application can use this signal to control the data bus flow of EDAT. |
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