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Notes: 11. tPD iS measured at l.5V for VDD = 3.3V and at l.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V-2.OV. 12. tLOCK iS the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits 13. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.