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PBMSH25M Datasheet

D0-15
Dim Min Max
A 25.40
B 5.50 7.62
c O686 0.889
D 2.60 3.6
All Dimensions in mm


PBMSH25M on stock
The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24LC21A which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-3).

VDD:5V.VRE,:2V.inputCode:4095
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