PBL386201 Datasheet| Characteristic | Symbol | Test condition | Min | Typ. | Max | Unit | | Drain-source breakdown voltage | BVDSS | VGS=OV, ID=50cCA | 650 | | | V | | Zero gate voltage drain current | IDSS | VDS=Max., Rating, VGS=OV | | | 50 | | | VDS=0.8Max., Rating, VGS=OV, Tc=125IC | | | 200 | | | Static drain-source on resistance(note) | RDS(ON) | VGS=10V, ID=0.5A | | 1.25 | 1.6 | l | | Forward transconductance (note) | gfs | VDS=50V, ID=0.5A | 3.0 | | | S | | Input capacitance | Ciss | VGS=OV, VDS=25V, | | 1 600 | | pF | | Output capacitance | Coss | f=lMHz | | 31 0 | | | Reverse transfer capacitance | Crss | | 120 | | | Turn on delay time | td(on) | VDD=0.5BVDSS, ID=1.OA | | 25 | | nS | | Rise time | tr | (MOSFET switching time are essentially | | 55 | | | Turn o delay time | td(off) | independent of | | 80 | | | Fall time | tf | operating temperature) | | 50 | | | Total gate charge (gate-source+gate-drain) | Qg | VGS=10V, ID=1.OA, VDS=0.5BVDSS (MOSFET | | | 72 | nC | | Gate-source charge | Qgs | switching time are essentially independent of | | g3 | | | Gate-drain (Miller) charge | Qgd | operating temperature) | | 29.3 | | | | | | | | |
PBL386201 Price| Parameter | Symbol | Rating | Unit | | Reverse voltage (DC) | VR | 30 | V | | Repetitive peak reverse-voltage | VRRM | 30 | V | | Peak forward | Single | IFM | 300 | mA | | current | Double | 225 | | Average forward | Single | IF(AVl | 200 | mA | | current | Double | 150 | | Non-repetitive peak | Single | IFSM | 1 | A | | forward-surge-current '2 | Double | 0 75 | | Junction temperature | Ti | 150 | oC | | Storage temperature | Tstg | -55 to +150 | OC | | | | | |
PBL386201 on stock| | | | | | | | C,OMMON | | | | | | | | | | | | | | | | | EMITTER | | | | | | | | | Te = 250C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | t 7 | = | = 151 | | | | | | | | | | | | | | | | | | | L | | | | | | | | | dU | | | | | | | | | | | | | | | | | | | | | | | | | | | |
The TC7WH125 is an advanced high speed CMOS DUAL BUS BUFFERS fabricated with silicon gate CMOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The require 3-state control input G to be set high to place the output into the impedance. This device is designed to be used with 3-state memory address drivers, etc. An input protection circuit ensures that o t0 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V t0 3V system and two supply system such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
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