| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
PBL38122 Datasheet
PBL38122 Price Each DAC has an input latch which receives data from the data bus, and a DAC latch which receives data from the input latch. The analog output of each DAC corresponds to the data in its DAC latch. One of the eight input latches is addressed by the address lines A(2:0) according to Table l. While Cs and WR are low, the addressed input latch is transparent and the seven other input latches are latched. Bringing cs or WR high latches data into the ad- dressed input latch. While LDAC iS low, all eight DAC latches are transparent. Bringing LDAC high latches data into the DAC latches.While cs, WR and LDAC are low, both latches are transparent and input data is transferred directly to the selected DAC.While CLR iS low, all DAC out- puts are set to their corresponding RGNDxx. Bringing CLR high returns each DAC's output to the voltage correspond- ing to the data in each DAC latch. PBL38122 on stock t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC_. 2. Differential voltages are at IN+ with respect to IN-. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or +15 V, whichever is less. 4. The output may be shorted to ground or either power supply. 5. The package thermal impedance is calculated in accordance with JESD 51-7. total reference voltage across it. Tap points across these re- sistors can be connected, in groups of sixteen, to the sixteen comparators at the right of the diagram. On the left side of the diagram is a string of seven resistors connected between VREF and VREF-. Six comparators com- pare the input voltage with the tap voltages on this resistor string to provide a low-resolution "estimate" of the input volt- age. This estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right. Note that the comparators on the left needn't be very accurate; they simply provide an estimate of the input volt- age. Only the sixteen comparators on the right and the six on the left are necessary to perform the initial six-bit flash con- version, instead of the 64 comparators that would be re- quired using conventional half-flash methods. To perform a conversion, the estimator compares the input voltage with the tap voltages on the seven resistors on the left. The estimator decoder then determines which MSB Lad- der tap points will be connected to the sixteen comparators on the right. For example, assume that the estimator deter- mines that VIN iS between 11/16 and 13/16 0f VREF. The es- timator decoder will instruct the comparator MUX to connect the 16 comparators to the taps on the MSB ladder between 10/16 and 14/16 0f VREF. The 16 comparators will then per- |
