PBL3798QN Datasheet NOTES 1In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%. 2Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications) Specifications subject to change without notice. PBL3798QN Price| Symbol | Characteristic | Min | Typ. | Max | Units | Test Condition | | BVoss | Drain-Source Breakdown Voltage | -200 | | | v | VCS=OV,ID=-250jiA | | ABV/ATj | Breakdown Voltage Temp. Coeff. | | -0.2 | | V/oC | ID=-250IJA See Fig 7 | | VGS(th) | Gate Threshold Voltage | -2.0 | | -4.0 | v | VDS=-5V,ID=-25011A | | | Gate-Source Leakage , Forward | | | -100 | | VGS=-30V | | IGSS | Gate-Source Leakage , Reverse | | | 100 | nA | VGS=30V | | | | | | -10 | | VDS=-200V | | IDSS | Drain-to-Source Leakage Current | | | -100 | LA | VDS=-160V,TC=1250C | | RDScon) | Static Drain-Source On-State Resistance | | | 3.0 | Q | VCS=-10V,ID=-0.7A 0 | | 9fs | Forward Transconductance | | 1.0 | | Q | VDS=-40V,ID=-0.7A 0 | | Cl | Input Capacitance | | 220 | 285 | pF | VGS=OV,VDS=-25V,f =1MHz | | Co | Output Capacitance | | 45 | 65 | | C | Reverse Transfer Capacitance | | 16 | 25 | See Fig 5 | | td(on) | Turn-On Delay Time | | 10 | 30 | | | | tr | Rise Time | | 20 | 50 | VDD=-100V,ID=-1.75A, | | td(off) | Turn-Off Delay Time | | 27 | 65 | ns | RG=18 Q | | tf | Fall Time | | 12 | 35 | See Fig '13 0@ | | Qg | Total Gate Charge | | 9 | 11 | | VDS=-160V,VGS=-10V, | | Qg | Gate-Source Charge | | 1.8 | | nC | ID=-1.75A | | Qgd | Gate-Drain( " Miller " ) Charge | | 4.8 | | See Fig 6 & Fig '12 0@ | | | | | | | |
PBL3798QN on stock Exposed Pads The TSSOP-EP package has an exposed pad on the bottom of the package. This pad is electrically connect- ed to GND and should be connected to the ground plane for improved thermal conductivity. Do not route signals under this package. | | | | | | | | | | | | | | | | | Ic | )M'off'/ | | | lcor | l(on) | ____ - | | | | | | | | | | | | | | | | | | 25 45 | | | | | |
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