PBL3726-10 Datasheet| PARAMETER | CONDITIONS | MIN | TYP | MAX | UNITS | | DC SPECIFICATIONS (i) VOH Output Voltage High, OUTp or OUTN VOL Output Voltage Low, OUTp or OUTN IVODI Output Differential Voltage, IOUTp - OUTNI VOs Output Offset Voltage(2) Co Output Capacitance(3) lqVODI Change in IVODI Between o and 1 QVos Change Between o and 1 ISOUT Output Short-Circuit Current ISOUTNP Output Current | RLOAD = iool+1% See LVDS Timing Diagram, Page 7 RLOAD = iool+1% RLOAD = iool+1% RLOAD = iool+1% See LVDS Timing Diagram, Page 7 VCM = 1.5V RLOAD = iool+1% RLOAD = iool+1% Drivers Shorted to Ground Drivers Shorted Together | 900 300 1100 | 1375 1025 350 1200 4 | 1500 400 1300 25 25 40 12 | mV mV mV mV pF mV mV mA mA | | DRIVER AC SPECIFICATIONS Clock LVDS Clock Duty Cycle Minimum Data Setup Time(4)(5) Minimum Data Hold Time(4)(5) tRISE/tFALL VOD Rise Time or VOD Fall Time | 6 x ADCLK (LCLKp, LCLKN) lo = 2.5mA lo = 3.5mA lo = 4.5mA lo = 6mA | 45 | 50 650 650 400 250 200 150 | 55 | % ps ps ps ps ps ps | | | | | | | PBL3726-10 Price| | | | Limits | | | Symbol | Parameter | Test Conditions | Min | Typ | Max | Unit | | BVDSS | Drain-Source Breakdown Voltage | VGS=OV, ID=-250uA | -30 | | | V | | ABVDSSTj | Breakdown Voltage Temperature Coefficient | Reference t0 250C, ID=-lmA | | -0.02 | | V/oC | | | Static Drain-Source | VGS=-10V, ID=-18A | | | 28 | | | RDScON) | On-Resistance (Note 2) | VGS=-4.5V, ID=-14A | | | 50 | mQ | | VGS(th) | Gate Threshold Voltage | VDS= VGS, ID=-250uA | 1 | | | V | | 9fs | Forward Transconductance | VDS=-10V, ID=-18A | | 20 | | S | | | Drain-Source Leakage Current(TJ=250C) | VDS=-30V, VGS=OV | | | 1 | uA | | lDSS | Drain-Source Leakage Current(TJ=1500C) | VDS=-24V, VGS=OV | | | -25 | | IGSS | Gate Source Leakage | VGS=+20V | | | ±100 | nA | | Qa | Total Gate Charge (Note 2) | ID=-18A | | 14 | 22 | | | Qas | Gate-Source Charge | VDS=-24V | | 3 | | nC | | Qad | Gate-Drain ("Miller") Charge | VGS=-4.5V | | 9 | | | tdfonl | Turn-On Delay Time (Note 2) | VDS=-15V | | 12 | | | | l | Rise Time | ID=-18A | | 56 | | nS | | td(off) | Turn-Off Delay Time | RG=3.3Q, VGS=-10V | | 30 | | | tf | Fall-Time | RD=0.8Q | | 57 | | | Ciss | Input Capacitance | VGS=OV | | 915 | 1465 | | | Coss | Output Capacitance | VDS=-25V, | | 280 | | pF | | Crss | Reverse Transfer Capacitance | f=l.OMHz | | 195 | | | | | | | | | PBL3726-10 on stock| | | | III VGS(off | l =1 5V | | | | | | | | | | | | | | | V( | S(off) | =3 | | | i | | l | | | | | | | | | | 1 | R | | > | L | | Assume VDD = -15 V, VDS = -5 V 1 Av =1 gfsRR90s RL = 1lDV | | | | | | | | | | | |
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. Operation in little or big endian mode is configurable through internal registers. The COMI address bus is 16 bit wide allowing direct access of up t0 64K words of the DPRAM. Two chip select signals are provided to allow splitting of the 64k address space in two memory banks. Host Control Interface (HOCI) gives read and write access to the TSS901E configuration registers and to the DS-Iink channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral that generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's address space. Packets can be transmitted or received directly via the HOCI. In this case the Com- munication Memory (DPRAM) is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction. The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment can be configured for little or big endian mode through an external pin. Additionally the HOCI contains the interrupt signalling capability of the TSS901E by providing an interrupt output, the interrupt status register and interrupt mask register to the local CPU. A special pin is provided to select between control of the TSS901E by HOCI or by link. If control by link is enabled, the host data bus functions as a 32-bit general pur- pose interface (GPIO). Protocol Command Interface (PRCI) that collects the decoded commands from all PPUs and forwards them to external circuitry via 5 special pins. JTAG Test Interface that represents the boundary scan testing provisions specified by IEEE Standard 1149.1 0f the Joint Testing Action Group (JTAG). The TSS901 E' test access port and on-chip circuitry is fully compliant with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the TSS901E I/O pins. |