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PB10S4 Datasheet

Item	Symbo]	Value	Unit
j pz	VCBO	±130	V
j v4·	VCLD	±80	V
i-Z	VEBO	±7	V
^j pf	ICP	±8	A
j p	Ic	±4	A
	PD	15	W
	Tj	150
	Tstg	- 55+150

PB10S4 Price

Transmitter The transmitter accepts parallel data from the CPU and converts it to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the TxFIFO, the TxD output remains high and the TxEMT bit in the SR will be set t0 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character in the TxFIFO. In the 16X clock mode, this also re-synchronizes the internal lX transmitter clock so that transmission of the new character begins with minimum delay.
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Parameters	E-Iine	T0-39	DIL	Units
VDS Drain-source voltage	100	100	100	V
ID Continuous drain current (@ TA =250C)	0.32	0.32	0.32	A
ID Continuous drain current (@ Tc =250C)		0.85		A
IDM Pulsed drain current	6	6	3	A
VGS Gate-source voltage	+20	+20	+20	V
PD Max. power dissipation {@ TA =250Cl	0.7	0.7	0 85	W
PD Max. power dissipation (@ Tc =25aC)		5		W
Tj, Tstg Operating/storage temperature range	-55 to +150			oc

Following are S-Parameter graphs for both the high gain and the AMPS modes. Data was taken on a single "nominal" device at 2.8v Vdd. The reference planes were set at the end of the package pins. Note that the plots are almost identical for both modes.

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