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PB1008S Datasheet

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PB1008S Price

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PB1008S on stock

Parameter		Symbol	CC (DDR400@CL=3.0)		B3 (DDR333@CL=2.5)		A2 (DDR266@CL=2.0)		BO (DDR266@CL=2.5)		Unit	Note
Parameter		Symbol	Min	Max	Min	Max	Min	Max	Min	Max	Unit	Note
Row cycle time		tRC	55		60		65		65		ns
Refresh row cycle time		tRFC	70		72		75		75		ns
Row active time		tRAS	40	70K	42	70K	45	70K	45	70K	ns
RAS to CAS delay		tRCD	15		18		20		20		ns
Row precharge time		tRP	15		18		20		20		ns
Row active to Row active delay		tRRD	10		12		15		15		ns
Write recovery time		tWR	15		15		15		15		ns
Last data in to Read command		tWTR	2		1		1		1		tCK
	C L=2.0				7 5	12	7 5	12	10	12	ns
Clock cycle time	C L=2.5	tCK	6	12	6	12	7 5	12	7 5	12	ns
Clock cycle time	CL=3.0	tCK	5	10
Clock high level width		tCH	0 45	0.55	0 45	0.55	0.45	0 55	0.45	0 55	tCK
Clock low level width		tCL	0 45	0.55	0 45	0.55	0 45	0 55	0.45	0 55	tCK
DQS-out access time from CK/CK		tDQSCK	-0.55	+0.55	-0.6	+0.6	-0.75	+0.75	-0.75	+0.75	ns
Output data access time from CK/CK		tAC	-0.65	+0.65	-0.7	+0.7	-0.75	+0.75	-0.75	+0.75	ns
Data strobe edge to ouput data edge		tDQSQ		0.4		0.45		0.5		0.5	ns	22
Read Preamble		tRPRE	0.9	1 1	0.9	1.1	0 9	1.1	0 9	1.1	tCK
Read Postamble		tRPST	0.4	0.6	0 4	0.6	0 4	0.6	0 4	0.6	tCK
CK to valid DQS-in		tDQSS	0 72	1.28	0 75	1.25	0.75	1 25	0.75	1 25	tCK
DQS-in setup time		tWPRES	0		0		0		0		ns	13
DQS-in hold time		tWPRE	0 25		0 25		0.25		0.25		tCK
DQS falling edge to CK rising-setup time		tDSS	0.2		0 2		0 2		0 2		tCK
DQS falling edge from CK rising-hold time		tDSH	0.2		0 2		0 2		0 2		tCK
DQS-in high level width		tDQSH	0 35		0 35		0 35		0.35		tCK
DQS-in low level width		tDQSL	0 35		0 35		0 35		0 35		tCK
Address and Control Input setup time(fast)		tIS	0.6		0 75		0 9		0 9		ns	15, 17~19
Address and Control Input hold time(fast)		tIH	0.6		0 75		0 9		0 9		ns	15, 1719
Address and Control Input setup		tIS	0.7		0.8		1.0		1 0		ns	1619
Address and Control Input hold time(slow)		tIH	0.7		0 8		1 0		1 0		ns	1619
Data-out high impedence time from CK/CK		tHZ	-0.65	+0.65	-0.7	+0.7	-0.75	+0.75	-0.75	+0.75	ns	11
Data-out low impedence time from CK/CK		tLZ	-0.65	+0.65	-0.7	+0.7	-0.75	+0.75	-0.75	+0.75	ns	11
Mode register set cycle time		tMRD	10		12		15		15		ns
DQ & DM setup time to DQS		tDS	0.4		0 45		0 5		0 5		ns	jk
DQ & DM hold time to DQS		tDH	0.4		0 45		0 5		0 5		ns	jk
Control & Address input pulse width		tIPW	2.2		2 2		2 2		2 2		ns	18
DQ & DM input pulse width		tDIPW	1 75		1 75		1.75		1.75		ns	18
Exit self refresh to non-Read command		tXSNR	75		75		75		75		ns
Exit self refresh to read command		tXSRD	200		200		200		200		tCK
Refresh interval time		tREFI		7.8		7.8		7.8		7.8	us	14
Output DQS valid window		tQH	tHP -tQHS		tHP -tQHS		tHP -tQHS		tHP -tQHS		ns	21
Clock half period		tHP	tCLmin or tCHmin		tCLmin or tCHmin		tCLmin or tCHmin		tCLmin or tCHmin		ns	20, 21
Data hold skew factor		tQHS		O5		0.55		0 75		0 75	ns	21
DQS write postamble time		tWPST	0.4	0.6	0 4	0.6	0 4	0.6	0 4	0.6	tCK	12
Active to Read with Auto precharge command		tRAP	15		18		20		20
Autoprecharge write recovery + Precharge time		tDAL	(tWR/tCK) + (tRP/tCK)		(tWR/tCK) + (tRP/tCK)		(tWR/tCK) + (tRP/tCK)		(tWR/tCK) + (tRP/tCK)		tCK	23

DS1374C Only The DS1374C integrates a standard 32,768Hz crystal into the package. Typical accuracy at nominal VCC and 250C is approximately 10ppm. See Application Note 58 for information about crystal accuracy vs. temperature.

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