| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| P200CH10CJ0 | WESTCODE | 2008 | NEW IN STOCK | 158 |
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P200CH10CJ0 Datasheet ( A ) I n o A ' O V i O A i f l d i f l 0 ( y L U ) I n o l l N t j f l o a v o i P200CH10CJ0 on stock DEFINITIONS VF = Instantaneous forward voltage (pw = 300as, D = 2%). IR = Instantaneous reverse current . trr = Reverse recovery time (See Figure 9), summation of to + tb. to = Time to reach peak reverse current (See Figure 9). tb = Time from peak IRM to projected zero crossing of IRM based on a straight line from peak IRM through 25% of IRM (See Figure 9) QRR = Reverse recovery charge. CJ = Junction Capacitance. RejC = Thermal resistance junction to case. pw = pulse width. D = duty cycle. ID = 0.25 mA; VGS = 0 V Tj = 25 IC Tj = -55 IC ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 IC Tj = 175 IC Tj = -55 IC VDS = 55 V; VGS = OV Tj = 25 IC Tj = 175 IC VcS = +10 V; VDS = 0 V VGS = 10 V; ID = 25 A; Figure 7 and 8 Tj = 25 IC Tj = 175 IC The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter- face directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. |
