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P082A07 on stock| Input Operating Rage | CIN | Ro | co | RB | cB | Ripple |
| 0 t0 1.0 kHz | 0.02 VF | 6.8 kQ | O1 VF | 100 kQ | 100 VF | 1.0 mV |
| 0 t0 10 kHz | 0.002 pLF | 6.8 k92 | 0.01 u.F | 100 kQ | 10 VF | 1.0 mV |
| 0 t0 100 kHz | 200 pF | 6.8 k92 | 0.001 VF | 100 kQ | 1.0 VF | 1.0 mV |
| | | | | | |
| Memory Size | Ordering Code | Package | Operation Range |
| 512K | AT17LV512-10JC | 20J | Commercial (OIC t0 70IC) |
| AT17LV512-10JI | 20J | Industrial (-40IC t0 85IC) |
| 1M | AT17LV010-10JC | 20J | Commercial (OIC t0 70IC) |
| AT17LV010-10JI | 20J | Industrial (-40IC t0 85IC) |
| | | |
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protec- tion is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0." When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled.
