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Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that tRCD> tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFFl(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.