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suppliers of N4517061D and PDF data of N4517061D

Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
N4517061D	Signetics	PLCC	07+/08+		10000	ShenzhenChongshengElectronicsC.. Contact:Mr.Jackies Tel:86-755-83031502 Fax:86-755-81614542 Email: chongxonexport@hotmail.com
N4517061D	S		92		77	EMELECTRONICINTL.LTD. Contact:Ms.candychen Tel:86-755-82810220 Fax:86-755-82810359 Email: candychen@em-elect.com

N4517061D Datasheet

Multilayer construction also permits the routing of sen- sitive signal traces away from high-level, high-speed signal lines. To minimize the possibility of coupling noise into the receiver section, high-level, high-speed signals such as transmitter inputs and clock lines should be routed as far away as possible from the receiver pins.
N4517061D Price

Symbol	2SC2921	Unit
VCBO	160	v
VCEO	160	v
VEBO	5	v
Ic	15	A
IB	4	A
Pe	150(Tc=250C)	W
Tj	150	oc
Tstg	-55 to +150	oc

N4517061D on stock

Pin Name	Pin Function
l/00 ~ l/07 (K9XXG08XXM) l/00 ~ l/Ois (K9K4G16XOM)	DATA INPUTS/OUTPUTS The l/0 pins are used to input command, address and data, and to output data during read operations. The Il 0 pins float to high-z when the chip is deselected or when the outputs are disabled. 1/08 ~ l/015 are used only in X16 0rganization device. Since command input and address input are x8 0per- ation, 1/08 ~ 1/015 are not used to input command & address. 1/08 ~ 1/015 are used only for data input and output.
CLE	COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the l/0 ports on the rising edge of the WE signal.
ALE	ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
CE /CE1	CHIP ENABLE The CE / CEl input is the device selection control. When the device is in the Busy state, CE / CEl high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE / CEl control during read operation, refer to 'Page read' section of Device operation .
CE2	CHIP ENABLE The CE2 input enables the second K9K4GXXUOM
RE	READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the l/0 bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
WE	WRITE ENABLE The WE input controls writes to the l/0 port. Commands, address and data are latched on the rising edge of the WE pulse.
WP	WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
R/B1/ R/B2	READY/BUSY OUTPUT The R/B / R/B1 0utput indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE	POWER-ON READ ENABLE The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when PRE pin is tied to Vcc.
Vcc	POWER Vcc is the power supply for device.
Vss	GROUND
NC	NO CONNECTION Lead is not internally connected.

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
IDR IDRM VSD	Continuous reverse drain current Pulsed reverse drain current Diode forward voltage	IF = 22 A ; VGS = 0 V		1.3	22 88 1.7	A A V
trr Qrr	Reverse recovery time Reverse recovery charge	IF = 22 A; -dIF/dt = 100 A/ s; VGS = 0 V; VR = 30 V		60 0.25		ns

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