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Notes: 1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE Abort means a WRITE command is given, but no operation is performed. 3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements. 4. If an Ignore Clock Edge command occurs during a READ operation, the l/0 bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWl,BW2,BW3 and BW4) are HIGH. BWx = L means one or more byte write signals are LOW. 6. Bwienables WRITEs to Byte "a" (l/Oa pins); BW2 enables WRITEs to Byte "b" (l/Ob pins); BW3 enables WRITEs to Byte "c" (l/Oc pins); BW4 enables WRITEs to Byte "d" (l/Od pins). 7. The address counter is incremented for all Continue Burst cycles.
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