N2530-6V0C-RB-WF Datasheet| | Parameter | Min | Typ | Max | Units | Test Conditions | | BVDSS | Drain-to-Source Breakdown Voltage | 1 00 | | | V | VGS = OV,ID = l.OmA | | CBVDSS/arJ | Temperature Coefficient of Breakdown Voltage | | O10 | | V/oC | Reference t0 250C, ID = l.OmA | | RDS(on) | Static Drain-to-Source On-State | | | O30 | l | VGS = 10V, ID =3.OA | | Resistance | | | 0.345 | VGS =10V,ID = 4.5A | | VGS(th) | Gate Threshold Voltage | 2 0 | | 4.0 | V | VDS = VGS, ID =250UA | | 9fs | Forward Transconductance | 1 5 | | | S(1) | VDS > 15V,IDS =3.OA | | IDSS | Zero Gate Voltage Drain Current | | | 25 | | VDS=80V,VGS=OV | | | | 250 | | VDS =80V VGS = OV, Tj = 1250C | | IGSS | Gate-to-Source Leakage Forward | | | 1 00 | nA | VGS20V | | IGSS | Gate-to-Source Leakage Reverse | | | -100 | VGS-20V | | Qg | Total Gate Charge | | | 1 7 | | VGS =10V, ID= 4.5A | | Qg;s | Gate-to-Source Charge | | | 4O | nC | VDS =50V | | Qgd | Gate-to-Drain ('Miller') Charge | | | 7.7 | | td(on) | Turn-On Delay Time | | | 40 | | VDD =50\{ ID =4.5A, | | tr | Rise Time | | | 70 | RG =7.5 I | | td(offl | Turn-Off Delay Time | | | 40 | ns | | tf | Fall Time | | | 70 | | LS +LD | Total Inductance | | 6.1 | | nH | Measured from the center of drain pad to center of source pad | | Ciss | Input Capacitance | | 3 50 | | | VGS = OV, VDS = 25V | | Coss | Output Capacitance | | 1 50 | | pF | f = 1.OMHz | | Crss | Reverse Transfer Capacitance | | 24 | | | | | | | | |
N2530-6V0C-RB-WF Price Track: This is an analog control input that enables the output voltage to follow an external voltage. This pin becomes active typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage from o V up to the nominal set-point voltage. Within this range the output will follow the voltage at the Track pin on a volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage. The feature allows the output voltage to rise simultaneously with other modules pow- ered from the same input bus. If unused, this input should be connected to Vin. Note: Due to the under-voltage lockout feature, the output of the module cannot follow its own input voltage dztring power up. For more information, consult the related application note. N2530-6V0C-RB-WF on stock| PIN | 3YMBOL | UESCPON | | 19, 41, 46, 47 | AGND | Analog Negative Supply Voltage (Ground) | | 20, 42, 45, 48 | AVDD | Analog Positive Supply Voltage | | 39 | BIASJ | Full-scale Output Current Bias | | 22 | CLK | External Clock Input | | 21 | CLKC | Complementory External Clock Input | | 1, 3, 5, 7, 9, 13, 23 25, 27, 29, 31, 33, 35 | D9(13:O)A | LVDS Positive Input, data bits 13 through 0 D13A is most significant data bit (MSB) DOA is the least significant bit (LSB) | | 2, 4, 6, 8, 10, 14, 24 26, 28, 30, 32, 34, 36 | D(13:O)B | LVDS Positive Input, data bits 13 through 0 D13B is most significant data bit (MSB) DOB is the least significant bit (LSB) | | 16,18 | DGND | Digital Negative Supply Voltage (Ground) | | 38 | DLLOFF | High = DLL Off / Low = DLL On | | 15, 17 | DVDD | Digital Positive Supply Voltage | | 40 | EXTIO | Internal reference out put or external reference input. Requires a O.luf decou- pling capacitor to groind when used as reference output. | | 43 | IOUT1 | DAC current output. Full scale when all inputs are set t0 1. Connect reference side DAC load resistors to AVDD | | 44 | IOUT2 | DAC complimentory current output. Full scale when all inputs are set t0 0. Connect reference side DAC load resistors to AVDD | | 37 | SLEEP | Asynchronous hardware power down input. Active high. Internally pulldown. | | | |
1.4 Free-Running and Self-Clocking Modes For operation in the free-running mode an initializing pulse should be used, following power-up, to ensure circuit opera- tion. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and INTR node should be momentarily forced to logic low following a power-up cycle to ensure start up. The clock for the A/D can be derived from the CPU clock or an external RC can be added to provide self-clocking. The CLK IN makes use of a Schmitt trigger as shown in Figure 2.
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